The Impact of Gate Annealing on Leakage Current and Radio Frequency Efficiency in AlGaN/GaN High-Electron-Mobility Transistors

Abstract

Gallium Nitride (GaN) high-electron mobility transistors (HEMTs) are highly promising for high-frequency and high-power applications due to their superior properties, such as a wide energy bandgap and high carrier density. The performance of GaN HEMTs is significantly influenced by the interfacial states of the AlGaN barrier, and gate annealing has emerged as a key process for reducing leakage currents and enhancing DC/RF characteristics. This research investigates the impact of gate annealing on AlGaN/GaN HEMTs, focusing on two main aspects: leakage current reduction and improvements in DC and RF efficiency. Through comprehensive electrical analysis, including DC and RF measurements, the effects of gate annealing were experimentally evaluated. The results show a significant reduction in gate leakage current and noticeable improvements in DC/RF performance for the devices that underwent gate annealing. The study confirms that the annealing process can effectively enhance device performance by modifying the material properties at the gate interface.

1. Introduction

Among the many candidates for devices with high-frequency and high-power capabilities, Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) have received the most promising evaluations due to their superior properties originating from their wide energy bandgaps and high carrier densities [1,2,3,4,5]. The performance of GaN HEMTs is known to be significantly affected by the interfacial states of the AlGaN barrier [6,7,8,9,10,11,12,13,14]. Gate annealing, involving controlled thermal treatments, improves the electrical performance by influencing the atomic arrangement and defect state at the gate interface [15]. High-temperature treatment helps to anneal out dislocations and passivate surface states, resulting in a more stable and defect-free interface, which is critical for reducing leakage currents and improving charge transport efficiency [16,17,18]. In this context, this research focuses on the impact of gate annealing on two crucial aspects of AlGaN/GaN HEMTs—leakage current reduction [19,20,21] and DC/RF efficiency enhancement [22,23,24].

In this work, through a comprehensive analysis of electrical properties including DC and RF characteristics, the effects of the presence or absence of gate annealing were experimentally analyzed. As a result, there was a very significant reduction in gate leakage current, and some degree of DC/RF performance improvement has been repeatedly observed. From a process perspective, we present quantitative differences according to the gate annealing process, and through this analysis, we confirm that the annealing process facilitates the reconstruction of interface defects and the removal of impurities, leading to improved interface quality between the AlGaN barrier and the gate metal.

Two groups of wafers were processed identically to form GaN HEMTs with T-shaped gates. One group underwent gate annealing after gate metal deposition, while the other group did not. Immediately after the gate annealing, there was no significant difference in performance between the two groups. However, after all processing was completed, there was a notable difference, especially in terms of the gate’s leakage current.

2. Methods

AlGaN/GaN heterostructures grown on an SiC substrate by metal–organic chemical vapor deposition (MOCVD) were used. As shown in Figure 1a, a buffer-free structure using SweGaN QuanFINE was used [25], and the structure consisted of 1 nm of GaN cap, 10 nm of Al_0.3Ga_0.7N barrier, a 1 nm AlN insertion, 250 nm GaN channel, and an AlN nucleation layer. Two identical wafers, grown together under the same conditions, were used for this study. The sheet resistance, electron density, and the mobility of 2DEG were determined to be 302.3 ohm/sq, 9.63 × 10⁻¹² /cm², and 2194 cm²/v·s, respectively, for the first wafer, and 303.9 ohm/sq, 9.80 × 10⁻¹² /cm², and 2135 cm²/v·s for the second wafer. The source/drain Ohmic contact was formed with Ti/Al/Ni/Au evaporation and rapid thermal annealing at 780 °C for 30 s. The device was isolated by phosphorus ion implant, and then 90 nm of SiN was deposited on the device by plasma enhanced chemical vapor deposition (PECVD). Source and drain areas were opened by BOE etching and 50/200 nm of Ti/Au metal electrodes was deposited to form an interconnection. We formed a T-shaped gate structure with a gate foot of 150 nm width and a gate head of 600nm width using E-beam and ICP etching, followed by electrode deposition using Ni/Au metal. Subsequently, the wafers were divided into two groups: one that underwent annealing at 250 °C for 15 min, and one that did not. A second SiN layer of 250 nm was deposited by PECVD, and ICP was used to open the gate, source, and drain electrodes. Additional interconnection was formed with a second metal layer, and a 3.5 µm thick air-bridge was created using a plating process to form internal vias. Finally, the process was completed with the deposition of a 50 nm final passivation layer and the opening of the electrodes. Figure 1b shows the cross-sectional scanning transmission electron microscopy (STEM) image of the gate area in the completed device. Transconductance (gm) and gate leakage current were measured immediately after the formation of the T-gate structure, after the gate annealing process if performed, and after the process was completed.

3. Results and Discussion

3.1. DC Characteristics

To analyze the electrical characteristics, DC measurements and RF measurements were performed. In the case of DC measurements, the devices with and without gate annealing were tracked according to the process progression. For each case, we measured immediately after gate metal deposition, after annealing for annealed devices, and after all processes by using Keysight HP4142. In each situation, we applied a drain voltage of 10 V and swept the gate voltage from −5 V to 1 V to obtain the Id-Vg curve and gm-Vg curve. Then, we applied a gate voltage of −5 V to turn off the channel and swept the drain voltage from 0 to 40 V to extract the gate leakage current and drain leakage current. Figure 2 is a graph of transconductance measured by applying a drain voltage of 10 V and varying the gate voltage from −5 V to 1 V.

Gate annealing was performed on one device and not on another. In the case of the device where gate annealing had not been performed, the maximum transconductance was measured as 491 mS/mm after the gate metal was deposited, and 475 mS/mm after all processes were completed. A slight decrease in maximum transconductance was observed. On the other hand, in the case of the device where gate annealing had been performed, the maximum transconductance was measured as 476 mS/mm after the gate metal was deposited, 451 mS/mm after gate annealing process, and 489 mS/mm after all processes. The maximum transconductance decreased after gate annealing, but increased after the process was completed compared to the initial value. This suggests that it exhibits a different behavior compared to devices that were not annealed.

The threshold voltage (V_th) was measured by the constant current method, with a criterion of 1mA/mm. For the device without gate annealing, the threshold voltage was measured as −1.48 V after gate metal deposition and −1.36 V after the completion of all processes. For the device with gate annealing, the threshold voltage was measured as −1.91 V after gate metal deposition, −1.69 V after annealing, and −1.75 V after the completion of all processes. Although there was an initial difference in the threshold voltage between the two devices after gate metal deposition due to process variations, the threshold shift was 0.12 V for the former and 0.16 V for the latter during the process.

Figure 3 shows the drain current change according to the gate bias voltage. Even when directly comparing the drain current, the difference is significant. In particular, for devices that did not undergo gate annealing, the off-state current at the end of the process was about 10 times higher than after gate metal deposition. However, for devices that underwent gate annealing, there was no significant difference. When the off-bias current is defined as V_gt = V_gs − V_th = −1 V, the off-bias current for the device without gate annealing was measured at 2.31 μA/mm after gate metal deposition and 31.9 μA/mm after the completion of all processes. For the device with gate annealing, the off-bias current was measured at 1.44 μA/mm after gate metal deposition, 1.44 μA/mm after annealing, and 3.19 μA/mm after the completion of all processes.

Figure 4 shows the gate leakage current change according to the drain bias for each case. In terms of leakage currents, a gate voltage of −5 V was applied, and the drain voltage was increased from 0 V to 40 V. For the wafer without annealing, when a drain voltage of 40 V and a gate voltage of −5 V were applied, the gate leakage current was measured at −5.36 μA/mm after gate metal deposition, and at −48.3 μA/m after the completion of the front-end process. For the wafer with annealing, the gate leakage current was measured at −5.93 μA/mm after gate metal deposition, −5.20 μA/mm after annealing, and −9.34 μA/mm after the completion of the front-end process.

The DC characteristics of AlGaN/GaN HEMTs with and without gate annealing were evaluated and compared in Table 1 through transconductance, threshold voltage (V_th), and leakage current measurements. The transconductance (gm) results revealed that for the device without gate annealing, there was a slight decrease in gm after the full process (from 491 to 475 mS/mm). However, the device with gate annealing showed a more dynamic behavior, where gm decreased after annealing but ultimately increased beyond the initial value after all processes were completed (from 476 to 489 mS/mm). This suggests that gate annealing may influence charge trapping at the gate interface, potentially improving the charge trapping dynamics and interface quality after the final process steps [26,27,28].

Gate leakage current showed significant differences. The device without gate annealing exhibited a dramatic increase in leakage current after the process (from −5.36 μA/mm to −4.83 μA/mm), likely due to increased charge trapping at the interface. In contrast, the annealed device maintained relatively stable leakage currents, with a moderate increase (from −5.93 μA/mm to −9.34 μA/mm), suggesting that gate annealing helps suppress the effects of charge trapping, reducing defects and improving the gate interface.

3.2. RF Characteristics

Afterward, the S-parameters within the frequency range of 0.5 to 50 GHz were evaluated using a Keysight N5245A microwave network analyzer, with gate voltage (V_g) set to 0 V and drain voltage (V_d) set to 0.8 V for the same device. The RF performance, including current gain (h21) and maximum stable/available gain (MSG/MAG), is shown in Figure 5. Using the above parameters, the cut-off frequency (ft) and the maximum frequency (fmax) were extracted. Similar to the DC measurements, both the device with gate annealing and the device without gate annealing were measured separately. Measurements were taken after all front-end processes were completed, and the results showed that the device without gate annealing had an ft of 48.87 GHz and fmax of 103.8 GHz, while the device with gate annealing had an ft of 52.98 GHz and fmax of 106.4 GHz. The improvements in RF efficiency were also notable. The RF efficiency increased by approximately 8.4%, as indicated by the enhanced power gain and reduced signal loss in high-frequency measurements. This improvement can be attributed to the better quality of the gate interface and reduced defect densities, which enhance carrier mobility and reduce scattering. The improved RF efficiency suggests that annealing can play a crucial role in optimizing HEMT performance for communication systems and other RF applications [17,22].

These results provide strong evidence for the beneficial effects of gate annealing on the performance of AlGaN/GaN HEMTs. Through a systematic measurement and analysis of the electrical characteristics before and after annealing, we have shown substantial improvements in key performance metrics. The process significantly decreases gate leakage currents, as demonstrated by the lower leakage in annealed devices compared to those without annealing. Furthermore, the improvements in RF performance, such as increased cut-off frequency (ft) and maximum frequency (fmax), emphasize the role of annealing in optimizing device efficiency for high-frequency applications.

4. Conclusions

The observed improvements in the I_d-V_g and gm-V_g curves can be attributed to the annealing process reducing interface trap densities at the gate interface and within the GaN layer. The increase in peak transconductance and shift in threshold voltage indicate a more efficient channel formation and reduced scattering of charge carriers. This suggests that annealing helps in passivating surface states and repairing lattice damage caused during fabrication. The resulting improvement in carrier transport leads to better device performance, as reflected in the enhanced I_d-V_g and gm-V_g characteristics. The significant reduction in gate and drain leakage currents post-annealing further supports this hypothesis. By decreasing the density of trap states and defects, the annealing process effectively minimizes leakage paths, enhancing the overall electrical integrity of the HEMTs. These findings underscore the importance of optimized annealing in the fabrication process, offering a pathway to achieving higher performance in RF applications. The reduced leakage currents contribute to lower power consumption and improved thermal management, which are critical for high-power devices.

While this study provides significant insights into the impact of gate annealing on GaN HEMTs, there are further characterization techniques that could deepen the understanding of the underlying mechanisms and enhance the overall analysis. For instance, multi-frequency C–V measurements could be employed to quantitatively assess the interface trap densities in devices with and without gate annealing, providing a more detailed evaluation of the gate interface’s quality. Additionally, load-pull measurements could be conducted to investigate the large-signal behaviors of GaN HEMTs, offering a more comprehensive analysis of the devices’ RF performance under high-power conditions. Also, stress testing under high-temperature and high-voltage conditions could be performed to assess the long-term reliability of the gate-annealed devices. These techniques present opportunities for future work and could provide further validation of the beneficial effects of gate annealing on device reliability and efficiency.

Author Contributions

Conceptualization, J.K.; methodology, J.K.; validation, J.K. and G.L.; Formal Analysis, J.Y.P., B.-G.M. and K.C.; Investigation, J.K., J.J. and H.-G.J.; Data Curation, J.K., J.J., W.C. and J.-M.L., writing—original draft preparation, J.K.; supervision, B.-G.M. and D.-M.K.; project administration, D.-M.K. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

The data presented in this study are available on request from the corresponding author.

Conflicts of Interest

The authors declare no conflicts of interest.

Footnotes

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Figures and Table

Figure 1. (a) Structure of GaN HEMTs, (b) cross-sectional scanning transmission electron microscopy (STEM) image of GaN HEMTs, and (c) process flow chart.

Figure 2. Graph of transconductance vs. gate bias voltage as process progresses, (a) without gate annealing process and (b) with gate annealing process.

Figure 3. Graph of drain current vs. Vgt as process progresses, (a) without gate annealing process and (b) with gate annealing process. X-axis is Vgt = Vgs − Vth.

Figure 4. Graph of gate leakage current vs. drain bias voltage as the process progresses, (a) without gate annealing process and (b) with gate annealing process.

Figure 5. Graph of the RF performance, including current gain (h21) and maximum stable/available gain (MSG/MAG), (a) without gate annealing process and (b) with gate annealing process.

Table 1

Transconductance, gate leakage current, and threshold voltage (V_th) according to the wafer and process. Wafer 1 indicates the device which did not undergo the gate annealing process, while wafer 2 did undergo the process. Transconductance was measured by applying a drain voltage of 10 V, and gate leakage current was measured by applying a drain voltage of 40 V and gate voltage of −5 V.

Device	Status	gm (mS/mm)	Ig.leak (μA/mm)	Vth (V)	Id.off (μA/mm)
Wafer 1	As deposited	491	−5.36	−1.48	0.231
Wafer 1	After all processes	475	−48.3	−1.36	3.19
Wafer 2	As deposited	476	−5.93	−1.91	0.144
Wafer 2	Gate annealing	451	−5.20	−1.69	0.144
Wafer 2	After all processes	489	−9.34	−1.75	0.319

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