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We report a sequential two-step vapor deposition process for growing mixed-dimensional van der Waals (vdW) materials, specifically Te nanowires (1D) and MoS\(_2\) (2D), on a single SiO\(_2\) wafer. Our growth technique offers a unique potential pathway to create large scale, high-quality, defect-free interfaces. The assembly of samples serves a twofold application: first, the as-prepared heterostructures (Te NW/MoS\(_2\)) provide insights into the atomically thin depletion region of a 1D/2D vdW diode, as revealed by electrical transport measurements and density functional theory-based quantum transport calculations. The charge transfer at the heterointerface is confirmed using Raman spectroscopy and Kelvin probe force microscopy (KPFM). We also observe modulation of the rectification ratio with varying applied gate voltage. Second, the non-hybrid regions on the substrate, consisting of the as-grown individual Te nanowires and MoS\(_2\) microstructures, are utilized to fabricate separate p- and n-FETs, respectively. Furthermore, the ionic liquid gating helps to realize low-power CMOS inverter and all basic logic gate operations using a pair of n- and p- field-effect transistors (FETs) on Si/SiO\(_2\) platform. This approach also demonstrates the potential for unifying diode and CMOS circuits on a single platform, opening opportunities for integrated analog and digital electronics.