Advancing packaging technology: computational fluid dynamics modeling for capillary underfill encapsulant in multi-chip heterogenous packages

Abstract

Purpose

The purpose of this study is to investigate the dynamics of capillary underfill flow (CUF) in flip-chip packaging, particularly in a multi-chip configuration. The study aims to understand how various parameters, such as chip-to-chip spacing (S12), chip thickness (tc) and others, affect the underfill flow process. By using computational fluid dynamics (CFD) simulations and experimental studies, the goal is to provide insights into understanding the dynamics of CUF in heterogeneous electronic packaging.

Design/methodology/approach

The paper introduces a CFD analysis and experimental study on CUF in a multi-chip configuration, aiming to understand underfill flow dynamics. A 3D geometry models of multi-chip arrangement are created using computer-aided design (CAD) software. After that, the CAD models are meshed and simulated in Ansys Fluent using incompressible and non-Newtonian fluid properties. The study maintains S12 of 2.86 and tc of 22.29 between experimental and simulation data for results validation. Next, a various of S12 values (1.14, 2.86, 5.71, 8.57, 14.29 and 20) which focus on tc of 22.29 have been investigated. Further studies have been conduct using S12 of 5.71 and tc of 8.00, 14.29 and 22.29.

Findings

Results show a strong correlation between simulation and experiment which validate the correctness and robustness of simulation. Further parameter’s studies using simulation for various of S12 indicated that higher S12 values lead to faster flow. This effect is due to large underfill weight from reservoir able to flow into S12 region which contributed to higher mass momentum movement. Furthermore, the effect of various of tc shows that the thicker the chip the faster the underfill to flow in S12 region.

Research limitations/implications

The intentional exclusion of solder bump pattern arrangements from the experiment and simulation may limit the study's ability to fully understand the impact of solder bump patterns on underfill flow. Therefore, more parameters can be investigated such as solder bump pattern, underfill weight and dispense pattern in the future using CFD.

Practical implications

The manuscript provides a comprehensive examination of the contributions of CFD to the advancement of knowledge regarding CUF phenomena in heterogeneous electronic packaging assemblies. Moreover, it delineates the utilization of CFD methodologies to assess the influence of chip-to-chip spacing (S12) and the thickness of the chip (tc) on the underfill flow characteristics.

Originality/value

This paper fulfills an identified need of computational fluid dynamics method to study capillary underfill flow dynamics in heterogenous electronic packaging.

1. Introduction

As the demand for smaller, faster and more powerful electronic devices continues to rise, flip-chip packaging has emerged as a key technology to meet these demands. This packaging technique offers several advantages over traditional packaging methods, including improved electrical performance, lower parasitic capacitance and higher thermal conductivity (Fang, 2018; Chai and Wu, 2001). These benefits are particularly important as maintaining Moore's Law projection, and the industry seeks innovative ways to enhance performance and functionality (Hsieh et al., 2017). One of the key drivers behind the adoption of flip-chip packaging is the trend toward heterogeneous integration (HI). HI involves integrating various components, such as processors, RAM and storage, into a single system to achieve higher I/O density, interconnect speeds and functionality (Chen et al., 2021; Kim, 2021). Techniques such as chip stacking, chiplets and system-on-a-chip (SoC) enable HI, allowing for component optimization and improved performance and power efficiency as shown in Figure 1. HI also facilitates the development of modular and scalable systems, enabling advancements in artificial intelligence (AI) and machine learning (ML).

Despite its many benefits, HI also presents challenges. Efficient component communication, ensuring system reliability and security are among the key challenges associated with HI. The complexity of integrating varied materials, processes and technologies in HI can increase the propensity for defects. For example, differences in the coefficient of thermal expansion (CTE) between components can lead to mechanical stresses during temperature changes, potentially causing delamination or cracking (Zhang et al., 2022a, 2022b). Addressing these challenges requires careful consideration of design, materials and manufacturing processes to ensure the reliability and performance of HI systems.

Traditionally, flip-chip ball grid array packaging has used a liquid underfill encapsulant to bridge the gap between the die and substrate, using capillary action to flow into the space and cure, thereby protecting the die and solder bumps (Zhang et al., 2022a, 2022b; Wakeel, 2021). This underfill material plays a critical role in reducing mechanical stresses that arise from the CTE mismatch between the die, solder bumps and the organic substrate (Wang et al., 2016; Yang, 2021). However, as the industry pushes for smaller bump diameters and pitches, the underfill material faces increased resistance to flow, requiring innovative strategies to manage its behavior (Wang, 2007). To address these challenges, researchers are exploring numerical methods to comprehensively analyze the dynamics of underfill flow, a necessity due to limitations in experimental visualization techniques. Figure 2 illustrates the growing interest and research focus on underfilling flow studies in the encapsulation process (Ng and Abas, 2022).

Various models have been developed to describe the behavior of underfill flow in flip-chip packaging, each offering insights into the complex underfill flow dynamics involved. Among these models are the Hele–Shaw (Young, 2011a, 2011b; Young, 2006), Washburn (Emerson and Jones Adkins, 1999; Wan et al., 2005a), power law (Young, 2011, 2011b; Wan et al., 2005b; Khor et al., 2012), cross viscosity (Xu et al., 2013; Khor et al., 2010a, 2010b) and Castro–Macosko models (Fang, 2018; Ng et al., 2016; Lo et al., 2021), each contributing to our understanding of the process. Wan et al., (2007) have contributed significantly to this field by developing an analytical model based on the power law constitutive Wang et al., 2009. Their model has demonstrated superior predictive capabilities compared to the traditional Washburn model, accurately forecasting flow front progression and filling times in both two parallel plates and flip-chip packaging scenarios. This alignment with experimental results underscores the model's efficacy and relevance. Notably, the power law constitutive equation is adept at capturing non-Newtonian fluid behavior, a feature absents in the Washburn model, which is confined to Newtonian fluids (Zhao et al., 2022). Wan et al. (2005) have also provided a thorough review of flip-chip packaging modeling, showcasing their two-dimensional finite element method analysis of underfill flow dynamics. By using advanced techniques such as the volume of fluid (VOF) method and incorporating power law constitutive equations with time-independent velocity boundary conditions, their model surpasses others in its accuracy and applicability. Young's research has further enriched our understanding by exploring the influence of viscosity on underfill flow in flip-chip encapsulation (Young, 2011). Their findings have revealed substantial effects of shear thinning and thickening behaviors on velocity profiles and filling speeds. Recent studies have also highlighted a growing interest in underfill simulations for multi-chip arrangements (Stencel et al., 2023a, 2023b), signaling the need for expanded investigation in this area. In this context, this article introduces a three-dimensional computational fluid dynamics (CFD) analysis and experimental study on capillary underfill flow (CUF) in a multi-chip configuration. The study includes chip-to-chip spacing (S) and chip thickness (t_c) to investigate the impact of these parameters toward underfill flow dynamics.

2. Methodology

Experiment and simulation setup

Figure 3 illustrates the CUF framework, which consists of input, process and output components. The input stage includes various parameters such as geometric dimensions, material properties and boundary conditions that influence the underfill flow process. Geometric inputs, like chip thickness (t_c), chip length (C_L), chip width (C_W), chip-to-chip spacing (S) and others, define the chip package design. Material properties for underfill, chips, substrate and solder bumps are critical inputs that replicate real-world conditions in simulations. Boundary conditions also play a vital role in mimicking real-world scenarios. These inputs collectively impact CUF, chip-to-chip (S) flow, edge flow and other process aspects.

A three-dimensional (3D) geometry of the chip arrangement is constructed using computer-aided design (CAD) software. This 3D CAD model undergoes meshing with Ansys Fluent Meshing, which is a sophisticated CFD simulation tool. Once the 3D CAD mesh is optimized, it is imported into Ansys Fluent for further processing. Within Ansys Fluent, specific naming selections are assigned to each surface, allowing for the precise input of contact angle values. Boundary conditions and material properties are meticulously set up in Ansys Fluent in preparation for CUF simulations. The simulations are conducted using VOF method. The fluid properties used are incompressible and non-Newtonian which reflecting behaviors observed at an approximate temperature of 110°C (Figure 4). To accurately represent the non-Newtonian shear thinning behavior of the fluid, the power law method is used, aligning with the data presented in Figure 4. All of variables in this paper using equation (1) to normalized, where X_normalized represents the normalized variable, X indicates the apparent variable and X_reference represents variable reference: (1) $$X_{normalized}=\frac{X}{X_{reference}}$$

Figure 5 presents a graph that plots normalized viscosity against normalized time, pinpointing the gelation time (t_gel) at a value of 372. As established in Section 3.2, all times reported in this study are normalized with reference to the moment the underfill touches Chip 3 (t_TC3) when the chip-to-chip spacing (S₁₂) is 2.86. It is important to note that both the experimental and simulation runs are conducted within a timeframe that falls below the identified gelation time. Additionally, transient dispense events, as illustrated in Figure 6, are replicated in the simulation using consistent dispense rates and weights to ensure accurate modeling of the underfill process.

Figure 7 presents a schematic diagram illustrating the chip arrangement setup for both experimental and simulation studies. In this investigation, the focus is on analyzing underfill flow in a configuration comprising three chips, excluding solder bump arrangements typically found in chip-substrate assemblies. The exclusion of bump pattern arrangements from the experiment and simulation is intentional to minimize their impact on CUF, with the intention of exploring their influence in future studies. Both the experimental and simulation setups involve two chips of the same size and one larger chip, with the gap between the substrate and chip (referred to as GCS) maintained constant for all cases studied in this paper. All dimensions are normalized with respect to GCS due to company confidential issues. The thickness of all chips (t_c1, t_c2 and t_c3) remains constant at 22.29. Chip 1 and Chip 2 share identical dimensions, with a width of 342.14 and a length of 222.14, while Chip 3 has a width of 714.29 and a length of 57.14. The initial point of underfill dispense is controlled at the same spot, with a dispense length (D_L) of 602 applied. The fiducial point is located in the middle region between Chip 1 and Chip 2. The dispense direction starts from Chip 1 to Chip 2. The chip-to-chip spacings (S₁₂ and S₁₃) are set at 2.86 and 5.71, respectively. The underfill weight is kept consistent across all case studies. The assembly incorporates glass as a substrate for visualization, with a camera capturing a perpendicular view of the CUF. To facilitate underfill flow, the glass is heated to approximately 105–110°C. Experimental images are post-processed using image tracking to enable comparison with simulation results. Additional simulations explore various S₁₂ values (1.14, 2.86, 5.71, 8.57, 14.29 and 20) by maintaining chip thickness of 22.29. Next, the effect of chips thicknesses is investigated with a focus on S₁₂ of 5.71. The detailed results of these investigations, including insights into the optimization of multi-chip arrangements to enhance CUF filling in electronic packaging, will be discussed in the results and discussion section.

3. Results and discussions

Fundamental of capillary underfill

In Figure 8, a schematic illustrates the flow of underfill material in a monolithic chip package. Initially, the underfill material flows from the reservoir region, creating flow in the GCS region (path 1), path 2 (right) and path 2 (left). As time progresses, the flow extends into path 3, leading to the formation of path 4 due to underfill supply in path 3. Path 3 is commonly referred to as chip edge flow. The differences in flow rates between path 3 and path 1 result in a distinctive “racing” effect (Abas et al., 2016; Wang et al., 2011).

The “racing” effect can cause uneven flow, contributing to higher differences between edge and mid flow (flow front delta), which can lead to issues such as the formation of macro voids. As more chips are added in heterogeneous integration (HI) packaging, the underfill flow becomes more complex, necessitating further studies to understand CUF behavior. Figure 9 presents a schematic diagram illustrating the basic concept of underfill flow in a multi-chip configuration. The values in the figures correspond to parameters used to explain the flow resistance in the GCS region for Chip 1 (RC₁) and Chip 2 (RC₂) in the x and z directions. These terms are used in the image to depict the scenario when solder bumps are present in an actual multi-chip package. Specifically, if the value of the flow resistance (RC) approaches infinity, it signifies a wall-like barrier where the underfill is unable to flow into that region. In Figure 9(a), the absence of S₁₂ results in underfill flow resembling a conventional monolithic chip, where it flows within the gap clearance spacing (GCS) region. Under GCS flow conditions, the RC₁ in the GCS region and RC₂ in the x and z directions are zero. Figure 9(b) depicts a two-chip arrangement with an S₁₂ of 5.71 without GCS. In this scenario, underfill cannot flow through Chip 1 and Chip 2 due to infinite RC_x and RC_z directions (no GCS). Figure 8(c) illustrates the combined GCS and S₁₂ flow, allowing underfill to flow through the GCS and S₁₂ regions simultaneously. This combined flow introduces complexity, emphasizing the importance of understanding underfill dynamics to prevent dispensing issues.

Experiment and simulation validations

As mentioned in the methodology section, the experimental and simulation results are compared for validation, using an S₁₂ value of 2.86. All times in this paper are normalized based on the time when the underfill touches Chip 3 (t_TC3) for an S₁₂ of 2.86. The images from the experimental and simulation setups, shown in Figure 10(a), are compared at normalized times (t_nz) of 0.04, 0.12 and 0.19. At t_nz of 0.04, the underfill starts to fill Chip 1, then passes through S₁₂ and Chip 2. Progressing to t_nz of 0.12, the underfill flow front in Chip 2 almost achieves the same flow front as Chip 1. By this time, a slightly faster underfill flow can be observed in S₁₂. This trend of accelerated flow within S₁₂ persists for next t_nz of 0.19. These results indicate a strong relationship between the experimental and simulation data. Figure 10(b) presents a comparison of normalized flow length (FL) versus normalized time (t_nz) for the experimental and simulation data. The FL is captured at the S₁₂ region, confirming a consistent correlation between the experiment and simulation. This validation supports the simulation results and warrants further investigation into the impact of S₁₂ parameters on CUF. Further study is conducted using simulation for a variety of S₁₂ (1.14, 2.86, 5.71, 8.57, 14.29 and 20) to analyze the differences in S₁₂ toward underfill flow. After that, a S₁₂ value of 5.71 is chosen to investigate the impact of chip thickness (t_c) on CUF in the vicinity of S₁₂.

Effect of capillary underfill flow on differences S₁₂

In this section, the investigation focuses on various S₁₂ values, including 1.14, 2.86, 5.71, 8.57, 14.29 and 20. Figure 11 illustrates the dispense pattern, with the dispense starting point consistently maintained across all cases. While there are slight variations in the dispense margin between the left and right sides for different S₁₂ values, these slight differences do not significantly impact underfill flow. This is attributed to the maintenance of consistent weight and dispense length across all S₁₂ cases.

Figure 12 illustrates the relationship between normalized FL and normalized time (t_nz) for different S₁₂ values. Notably, S₁₂ values of 14.29 and 20 exhibit a similar trend, achieving the fastest FL of 227.86, followed by 8.57 and 5.71. Subsequently, the trend for S₁₂ of 2.86 mirrors that of 1.14 until a t_nz of 0.62, after which it accelerates to achieve a FL of 227.86. This behavior can be attributed to the decrease in flow resistance with a larger gap.

In Figure 13(a), the change of FL per time (ΔFL/Δt_nz) of all S₁₂ values over t_nz are compared. The ΔFL/Δt_nz are calculated as shown in equation (2): (2) $$\frac{FL}{t_{nz}}=\frac{F{L}_{y_2}- F{L}_{y_1}}{t_{n{z}_{x_2}}- t_{n{z}_{x_1}}}$$where ΔFL/Δt_nz is change of flow length per time, $F{L}_{y_1}$ is flow length at initial point, $F{L}_{y_2}$ is flow length at final point, $t_{n{z}_{x_1}}$ is time at initial point and $t_{n{z}_{x_2}}$ is time at final point. The results show that the maximum ΔFL/Δt_nz occurs at the beginning and gradually decreases over time. Larger S₁₂ values contribute to higher ΔFL/Δt_nz due to lower flow resistance as the spacing increases. Figures 13(b) and (c), depict the ΔFL/Δt_nz for the centers of Chip 1 and Chip 2 against t_nz. The results indicate that the ΔFL/Δt_nz for both chips behave similarly across all variations of S₁₂. This implies that the differences in S₁₂ have a minimal effect on CUF at the GCS gap, possibly because there is enough underfill material available.

Figure 14 illustrates normalized time for underfill to touch Chip 3 (t_TC3), fully filling Chip 1 (t_FC1) and fully filling Chip 2 (t_FC2). The results for t_TC3 indicate a trend where increasing S₁₂ spacing typically leads to a reduction in t_TC3. However, an anomaly is observed when the S₁₂ is set to 20, at which point the t_TC3 starts to rise (slow flow). Based on the result, the trend for t_FC1 and t_FC2 across various S₁₂ are insignificant differences with averages of 0.72 and 0.76, respectively. Thus, an average of t_FC1 and t_FC2 are calculated which denote as ${\overline{t}}_{FC1-2}$. In contrast, t_TC3 is longest for S₁₂ of 1.14 with a value of 1.36, followed by 2.86 at 1.00, 5.71 at 0.68, 8.57 at 0.55, 14.29 at 0.39 and finally 20 at 0.45. Larger S₁₂ results in faster flow due to increased mass and momentum energy passing through the S₁₂ region. This trend has also been observed by C. Marushima et al. (2022), where the underfill flow starts to slow down when the spacing is larger. Timing gap (t_gap) between t_TC3 and ${\overline{t}}_{FC1-2}$ can be captured by using equation (2) whereby negative value will indicate ${\overline{t}}_{FC1-2}$ are faster than t_TC3 while positive value will indicate t_TC3 faster than ${\overline{t}}_{FC1-2}$: (3) $t_{gap}=t_{TC3}-{\overline{t}}_{FC1-2}$

The trend shows that S₁₂ of 5.71 almost have similar timing gap with value of −0.03. Meanwhile, t_gap for S₁₂ of 1.14 and 2.86 shows a positive value of 0.54 and 0.26, respectively. In contrast, t_gap for 8.57, 14.29 and 20 shows a negative value of −0.22, −0.39 and −0.23, respectively. This t_gap calculation can be applied for other multi-chip design to determine underfill filling and touch in the future.

Figure 15 presents the normalized pressure contour plot at the time when the underfill contacts Chip 3 (t_TC3) for a range of chip-to-chip spacings (S₁₂), including 1.14, 2.86, 5.71, 8.57, 14.29 and 20. The pressure values are normalized relative to the maximum capillary pressure observed. In the contour plot, negative values represent areas of capillary pressure. The data reveals that as the underfill progresses through the GCS region, the flow front is subjected to increased capillary pressure. The interplay between capillary-dominated and viscous-dominated flow is critical in shaping the underfill flow characteristics within both the S₁₂ and GCS regions, highlighting the importance of these forces in the overall underfill process (Teixidó et al., 2022).

Figure 16 illustrates an example of fluid flow in a fiber-reinforced polymer, explaining the differences between capillary-dominated and viscous-dominated flow. In capillary-dominated flow, the flow moves quickly in narrow spaces compared to viscous-dominated flow. This concept is relevant to this study, as the underfill can exhibit either capillary-dominated or viscous-dominated behavior depending on its properties.

In Figure 17, the normalized time delay (t_delay) against S₁₂ illustrates the timing captured when underfill passing through the end of Chip 1 and starting to touch Chip 3. A notable trend is observed, where S₁₂ of 1.14 experiences a higher t_delay at 1.38. This t_delay gradually decreases until S₁₂ of 14.29 and then begins to increase again at S₁₂ of 20. The increase in t_delay at S₁₂ of 20 suggests that the existing underfill weight may be insufficient to maintain weight supply in the S₁₂ region. This observation is further supported by Figure 18, which shows a noticeable difference in the mark location near the S₁₂ region between S₁₂ values of 14.29 and 20. Understanding this underfill filling pattern is crucial for optimizing the underfill process in heterogeneous integration.

Effect of capillary underfill flow on differences chip thickness

In this section, further investigations are continued using S₁₂ of 5.71 for various tc with value of 8.00, 14.29 and 22.29. Figure 19 illustrates the normalized FL captured at the S₁₂ region for t_c of 8.00, 14.29 and 22.29. Results indicate that t_c of 8.00 experiences a slower to achieve FL of 227.86 in the S₁₂ region compared to chip thickness (t_c) of 14.29 and 22.29, which take t_nz of 1.10, 0.88 and 0.68, respectively.

Figure 20 illustrates t_TC3, t_FC1 and t_FC2 versus t_c, showing a decreasing trend as the t_c becomes lower. This phenomenon is due to shorter chip thickness, reducing underfill weight from reservoir enter to the S₁₂ region while simultaneously reducing the underfill flow speed. In these cases, t_gap also been calculated same as previous section. The t_gap is higher for t_c of 8.00 with value of 0.25 as compared to 14.29 (0.14) and 22.29 (−0.03). More findings will be discussed in the next section, where the plot of change of FL per time (ΔFL/Δt_nz) versus chip thickness (t_c) is presented.

Figure 21 illustrates normalized time delay (t_delay) against chip thickness (t_c), observing the timing of underfill to flow through S₁₃ spacing. Based on results observed, there is a higher t_delay differences between t_c of 8.00 as compared to 14.29 and 22.29, with t_delays of 1.10, 0.88 and 0.68, respectively.

Figure 22 shows a normalized pressure contour plot for different tc. The maximum and minimum normalized pressure contours plotted are −1 and 1, respectively. Based on the image, higher underfill spreading in the reservoir region is captured for t_c of 8, followed by 14.29 and 22.29.

Figure 23(a) illustrates change of FL per time (ΔFL/Δt_nz) at the S₁₂ region for t_c of 8.00, 14.29 and 22.29. The results show a declining trend as the flow becomes slower and stops when the region is fully occupied with underfill material. The ΔFL/Δt_nz for a t_c of 22.29 is the fastest, with a maximum ΔFL/Δt_nz of 1141, followed by 14.29 (958) and 8.00 (732). Meanwhile, the maximum ΔFL/Δt_nz for Chip 1 [Figure 23(b)] and Chip 2 [Figure 23(c)] within various t_c with average value of 1050 and 946, respectively. Therefore, the major underfill flow effect has occurred in S₁₂ region as compared to the GCS region.

A higher t_c results in increased surface energy and, with the same underfill weight dispense, contributes more underfill weight flow inside the S₁₂ region which can be observed in Figure 24. The solid arrow shows how the underfill weight from reservoir flow in S₁₂ and denote differences between low and high t_c. Meanwhile, dotted arrow indicates underfill spreading whereby low t_c contributes to higher reservoir spreading. This information provides an overall understanding of how the t_c affects underfill flow in the S₁₂ region.

4. Conclusions

This study used a three-dimensional (3D) simulation to investigate the dynamics of CUF in chip packaging, a process that is challenging to monitor during the actual encapsulation. The simulation's accuracy was validated against experimental results to test its reliability and robustness. Intentionally, solder bump patterns were omitted from the chip arrangement in both the experimental and simulation setups to isolate their impact on CUF, with plans to address their influence in subsequent research. The study's methodology incorporated essential parameters such as geometric dimensions and material properties, which were pivotal in characterizing the chip package design and mirroring experimental conditions within the simulations. The comparative analysis between experimental and simulation data demonstrated a strong correlation, reinforcing the validity of the simulation approach. Due to confidentiality constraints, all dimensions and variables were normalized. The primary objective of this paper was to elucidate trends and fundamental aspects of CUF in heterogeneous electronic packaging, as well as to highlight the effectiveness of simulation in capturing the nuances of this process. The research specifically examined the effect of chip-to-chip spacing (S₁₂) on CUF. Results indicated that increased S₁₂ values typically resulted in faster flow, except for an S₁₂ of 20, where the flow decelerated due to insufficient underfill supply from the reservoir to the S₁₂ region. Subsequent analysis of different chip thicknesses, while maintaining an S₁₂ of 5.71, revealed that thicker chips promoted quicker underfill flow within the S₁₂ region. These findings are vital for refining the underfill process in electronic packaging, particularly within the framework of heterogeneous integration. The study underscores the importance of understanding underfill flow behavior to improve the reliability and performance of multi-chip electronic devices. The detailed analysis provided herein establishes a foundation for future research, which could further leverage simulation to analyze the impact of various factors on the dynamics of CUF.

The authors would like to greatly acknowledge Intel for funding this research. Intel’s engineer, Ooi Renn Chan, Li Wei, Edvin Cetegen, Leow Yen Houng and Omar Ali for supporting documents and sharing knowledge. Finally special thanks to Universiti Sains Malaysia engineering faculty management for their trust, support and encouragement.

Figure 1

Example of schematic diagrams of heterogeneous integration packaging (Zhang et al., 2022a, 2022b)

Figure 2

Statistical trends on the study of underfill flow in encapsulation process

Figure 3

Typical CUF simulation framework (Stencel et al., 2023)

Figure 4

Normalized viscosity versus shear rate (1/s) for underfill

Figure 5

Normalized viscosity versus normalized time for underfill

Figure 6

Simulation transients dispense setup

Figure 7

Schematic diagram three chips arrangement

Figure 8

Monolithic chip package underfill flow path (Kim et al., 2013)

Figure 9

Schematic diagram for two-chip series arrangement assembled with substrate

Figure 10

(a) Qualitative and (b) quantitative underfill fluid flow comparison between experiment and simulation

Figure 11

Dispense length configurations for variety of S₁₂ at normalized time (tnz) of 0.06

Figure 12

Normalized flow length (FL) against normalized time (t_nz) for varieties of S₁₂

Figure 13

Change of flow length per time (ΔFL/Δtnz) comparison plot in S₁₂, Chip 1 and Chip 2

Figure 14

Normalized time for touch Chip 3 (t_TC3), full fill Chip 1 (t_FC1) and full fill Chip 2 (t_FC2) versus S₁₂

Figure 15

Pressure contour plot for varieties of S₁₂ captured at normalized time underfill touch Chip 3 (t_TC3)

Figure 16

Differences of capillary dominated flow and viscous dominated flow (Teixidó et al., 2022)

Figure 17

Normalized time delay (tdelay) versus S₁₂

Figure 18

Simulation image captured at normalized time underfill touch Chip 3 (t_TC3) for S₁₂ of 14.29 and 20

Figure 19

Normalized flow length (FL) versus normalized time (tnz) for differences of chip thickness (t_c) at S₁₂ region

Figure 20

Normalized time for touch Chip 3 (t_TC3), fully fill Chip 1 (t_FC1) and Chip 2 (t_FC2) versus chip thickness (t_c)

Figure 21

Normalized time (t_nz) delay versus chip thickness (t_c)

Figure 22

Normalized pressure contour plot for various tc captured at normalized time when underfill touch Chip 3 (t_TC3)

Figure 23

Effect of Chip thickness toward underfill flow in S₁₂, Chip 1 and Chip 2 region

Figure 24

Side view comparison between chip thickness (t_c) 8.00, 14.29 and 22.29 at normalized time (t_nz) of 0.58