Design of Flexible Floating Point Processing Element (FFPPE) Based Fingerprint Authentication Model for Error Detection and Correction

Abstract

In communication systems, a proposed FPGA-based authentication setup utilizes an advanced version of the Golay alongside a Flexible Floating Point Processing Element (FFPPE) architecture to enhance fingerprint authentication accuracy. This study features a GOLAY code-integrated FFPPE design comprising various stages, including Timestamp (TS) output with a time to digital converter (TDC), a random number generator, and error correction components involving extended encoding and decoding processes, as well as fingerprint verification techniques. A novel compact integrated circuit (IC) is designed using FFPPE, which plays a key role in operations like multiplication, addition, and subtraction via an Arithmetic Logic Unit (ALU). The binary data structure is built on a Cyclic Redundancy Check (CRC) framework, using both encoders and decoders. This architecture enhances system security while optimizing circuit complexity. Within the error correction module, a polar code decoder tailored for extended Golay code is presented specifically for the fingerprint authentication system. The performance metrics are assessed in terms of look-up table (LUT) optimization, area, power, speed, circuit complexity, power consumption, slice count, clock frequency, false rejection rate (FRR), false acceptance rate (FAR), and total success rate (TSR), and these are compared against existing fingerprint authentication systems. A comparative evaluation between the proposed and existing methodologies is conducted based on multiple parameters to validate the efficacy of the proposed approach. Results indicate that the proposed approach surpasses traditional techniques in bolstering system security. Additionally, FPGA synthesis analysis is carried out across different FPGA families, including Virtex4, Virtex5, and Virtex7.