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In medium- and high-power-density applications, silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) are often connected in parallel increasing the current capability. However, the current sharing of paralleled SiC MOSFETs is affected by the mismatched technical parameters of devices and the deviated power circuit parasitic inductances, even if power devices are controlled by a single gate driver. This leads to unevenly distributed power losses causing different stress between SiC MOSFETs. As a result, unbalanced current sharing increases the probability of severe power switch(es) and system failures. For over a decade, the current imbalance issue between parallel-connected SiC MOSFETs has concerned the scientific community, and many methods and techniques have been proposed. However, most of these solutions are impossible to realize without the necessity of screening power devices to measure their technical parameters. Consequently, system costs significantly increase due to the expensive equipment for screening SiC MOSFETs. Also, transient current imbalance is the main concern of most papers, without addressing static imbalance. In this paper, an innovative approach is proposed, capable of suppressing both static and transient current imbalance between paralleled SiC MOSFETs, under both symmetrical and asymmetrical layouts, through an improved active gate driver and without the requirement for any power device screening process. Additionally, the proposed solution employs a self-sustaining algorithmic approach utilizing current sensors and a field-programmable gate array (FPGA). The functionality of the proposed solution is verified through experimental tests, achieving current imbalance suppression between two paralleled SiC MOSFETs, actively and autonomously.
