Inserted Window Recognition Based Capacitor Condition Monitoring Method for MMC Sub-Module with Nearest Level Modulation

Abstract

The sub-module capacitor is the most vulnerable component in a modular multilevel converter (MMC), and its aging poses a significant challenge to system stability. To accurately monitor capacitor aging, this article utilizes capacitor voltage fluctuations to recognize the inserted window for capacitance calculation using nearest-level modulation. Additionally, a time-slicing method is developed to improve accuracy. The proposed method, which combines the inserted window recognition method with the time-slicing algorithm, offers a simple, easy-implementation approach. Simulations and experimental results validate that the method achieves high accuracy (less than 0.5%). Moreover, it does not require additional sensors, precise extraction of switching signals, or interruption to the system’s normal operation, making it highly suitable for MMC systems with a large number of sub-modules. Furthermore, the proposed method also demonstrates strong robustness in dynamic conditions and can be extended to all sub-modules.

1. Introduction

The modular multilevel converter (MMC) has become one of the most popular topologies for high-voltage and high-power applications. Compared to other multilevel topologies, MMCs distinguish themselves by their modular structure, superior output waveforms, high reliability, and reduced losses [1,2]. Therefore, MMCs are widely applied in high-voltage direct current (HVDC) transmission [3], solid-state transformers [4], motor drives [5], static synchronous compensators [6], energy storage systems [7], etc.

The sub-module (SM) capacitor in MMCs serves as a crucial component in ensuring the stable operation of the converter. However, as shown in Table 1, capacitors are among the most vulnerable elements [8,9]. Failing to promptly detect capacitor aging can lead to a range of issues. As the capacitance decreases due to aging, it results in increased capacitor voltage fluctuations and distortion in the output voltage/current waveforms. This can cause severe consequences, including damage to the power semiconductor or even a system collapse [10]. Therefore, accurate and early diagnosis of capacitor aging in MMCs emerges as a critical topic.

Capacitor failures are typically accessed based on two critical electrical parameters: equivalent series capacitance (ESC) and equivalent series resistance (ESR) [11]. As capacitors degrade, their ESC decreases, and their ESR increases. The end-of-life (EOL) criteria of capacitors is defined as an ESC lower than the specified threshold (ESC_EOL) or an ESR higher than ESR_EOL. Aluminum electrolytic capacitors (Al-Cap) and metalized polypropylene film capacitors (MPPF-Cap) are two commonly used capacitors in MMCs. For Al-Cap, the ESC_EOL is 80% of the nominal capacitance C_0, and the ESR_EOL is 200% of the nominal resistance ESR₀. For MPPF-Caps, the ESC_EOL is 95% of C₀, while the ESR typically is too small to be measured (on the order of 1 × 10⁻⁵ Ω in MPPF-Caps, compared to 1 × 10⁻² Ω in Al-Caps). If the capacitor’s parameters reach the EOL criteria, it will be considered as a fault. Since even a 5% degradation is sufficient to lead to capacitor failure, achieving high accuracy in capacitance monitoring is critical.

MMC systems typically use pulse width modulation (PWM) or nearest level modulation (NLM) to control switching signals for AC and DC power conversion. In high voltage, high power applications, where MMCs must meet stringent transmission efficiency requirements, the number of inserted SMs can reach thousands. Thus, NLM has become the most widely used modulation method in these areas due to its easy implementation and low switching frequency [12]. However, this introduces a significant challenge for capacitance monitoring in MMC systems. With a large number of SMs, complex capacitance monitoring will bring a great computational burden. Therefore, it is crucial to develop a monitoring method that is both simple in approach and easy to implement.

An MMC system comes with two types of sensors: the SM capacitor voltage sensor and the arm current sensor. However, simply extracting data from these sensors does not directly enable capacitance calculation. To address this, early studies integrated additional capacitor current sensors into SMs, such as tunnel magnetoresistance [13] and Rogowski coil [14]. Despite their commendable accuracy, the addition of extra sensors increases both the volume and costs for the SMs.

In order to monitor capacitance without the need for additional sensors, most existing methods extract switching signals from the controller as supplementary data for calculation. By combining these switching signals with arm current to indirectly derive capacitor current, the method in [15] utilizes the inherent second-harmonic oscillations in the SM capacitor voltage/current for capacitance estimation. However, since this method relies on circulating current, it is only applicable to systems that do not employ circulating current suppression. In contrast, a recursive least squares estimator combined with a special low-pass filter is used in [16], reducing the noise effect in measurements. Similarly, reference [17] develops an improved data processing algorithm to enhance accuracy. An offset error compensation method is presented in [18] to ensure precision, while reference [19] discretizes the capacitor voltage/current to estimate capacitance. Additionally, in [20], real-time monitoring of aging capacitors is achieved by analyzing voltage variations at the rising and falling edges. However, all these methods focus on estimating the capacitance of each SM, whose complex calculations impose a significant computational burden on the MMC controller.

The method in [21] not only minimizes the burden but also introduces ESR monitoring for the first time. The approach establishes mathematical relationships between ESC, ESR, and the fundamental frequency component, enabling the ranking of SMs and focusing monitoring only on potentially anomalous SMs. Potential anomalies can also be detected based on the switching cycle [22] and switching frequency [23]. Furthermore, reference [24] proposes a capacitance self-updating voltage estimation method based on grouping measurements, which reduces the number of required voltage sensors.

The methods for extracting the switching signal require high accuracy on the controller; otherwise, errors in the switching signal can lead to significant computational inaccuracies. Although nearly all of the aforementioned methods incorporate parameter estimation algorithms or filters to improve accuracy, this results in a considerable computational burden. Recently, many scholars have explored methods without necessitating switching signals. For instance, by leveraging the start-up characteristics of the MMC, the SM can be simplified to an RC charging circuit. Capacitance estimation is then performed by analyzing the recorded charging waveforms [25]. However, this is an off-line method, effective only during the start-up phase. In [26], a different approach is adopted by establishing a relationship between the capacitance and the variation of capacitor voltage based on NLM. Meanwhile, reference [27] utilizes a phase-shifted carrier-based (PSC-PWM) modulation method, extracting the fundamental frequency components of capacitor voltage and current using a Fourier algorithm to estimate capacitance. In [28], capacitance is calculated using known circuit parameters by selecting only four key phase values within one fundamental period of capacitor voltage. Lastly, a new study introduces a closed-loop monitoring method for SM capacitance, achieving asymptotic convergence of estimation errors [29]. While these capacitance monitoring methods bypass the need for switching signals, they still require complex calculations.

In addition, several studies propose a method that involves a reference SM (RSM) with a known capacitance. The SM with the maximum capacitance is selected as the RSM and the monitored SM shares the same switching signals with the RSM. The capacitance of the unknown SM is then estimated by comparing their voltage differences [30]. Building on this, a study improves accuracy by directly charging the capacitance voltage in both the monitored SM and RSM from 0 to the rated value [31]. However, these methods require forced adjustment of switching signals, which may affect efficiency or interrupt steady operation. Additionally, the RSM capacitance needs to be accurately obtained in advance.

This paper fully leverages the internal information of MMC voltages/currents, which are already embedded in MMC systems. Capacitance is calculated by recognizing specific inserted windows from capacitor voltage and applying a time-slicing algorithm to enhance accuracy. This method eliminates the need for additional current sensors or other hardware, significantly simplifying the MMC design. Besides, the approach does not require the MMC to operate in the charging/discharging mode or bypass SM, thus avoiding any interruption to normal operation. Validated by extensive simulation and testing results, the proposed method achieves high accuracy with errors below 0.5%. It also has strong dynamic-tracking capability and scalability across all SMs.

The rest of this article is organized as follows: Section 2 introduces the basic principles of the MMC, its SMs, and its modulation method. Section 3 presents the proposed SM capacitance monitoring method. Simulation and experimental verification are carried out in Section 4 and Section 5, respectively. Finally, Section 6 encapsulates the findings and draws conclusions.

2. Topology and Operation Principle of MMC

Figure 1 illustrates a three-phase MMC topology with a half-bridge SM. Each phase comprises an upper arm and a lower arm, each consisting N identical SMs and an arm inductor in series. Furthermore, a detailed depiction of the SM structure is shown, which comprises two switches S_up and S_low, and a capacitor. The SM operates in two distinct modes: inserted (ON-state) or bypassed (OFF-state). When S_up = 1, S_low = 0, the SM is inserted to contribute to the output voltage, and the arm current flows through the capacitor. Conversely, if S_up = 0, S_low = 1, the SM is bypassed.

Consequently, the switching signal plays a crucial role in determining the capacitor voltage and current of SMs. Denoting S_aui as the switching signal of the ith SM, v_SM as the voltage of the SM capacitor, and i_aui as the current flows through the ith SM. The expressions of the ith SM capacitor voltage and SM current in the upper arm (phase-a) are given by Equations (7) and (8) [15,16,17,18,19,20,21,22,23,24]:

(1)$v_{SM}=\left\{\begin{array}{ll}0& \left(S_{up}=0,S_{low}=1\right)\\ v_{cap}& \left(S_{up}=1,S_{low}=0\right)\end{array}\right.$

(2)$i_{aui}=S_{aui}\cdot i_{arm}=\left\{\begin{array}{ll}{i}_{arm}& (S_{aui}=1, “\mathrm{ON}” \mathrm{state})\\ 0& (S_{aui}=0, “\mathrm{OFF}” \mathrm{state})\end{array}\right.$

As illustrated in Figure 2, the principle of NLM involves selecting the integer level nearest to the sinusoidal modulating waveform as the trigger signal. The orange dotted line represents the referenced modulating waveform, while the blue line represents the output level voltage. Subsequently, the corresponding number of SMs are inserted to generate a stepped waveform voltage that approximates the sinusoidal waveform. The modulation process is detailed as follows.

Take phase-a as an example, the output voltage can be expressed as [32]

(3)$u_{ao}={\displaystyle \frac{V_{dc}}{2}}{m}_a\cos \left(\omega t\right)$

where m_a represents the modulation index.

From the MMC mathematical model, the upper and lower arm voltages can be expressed as

(4)$\left\{\begin{array}{l}{u}_{pa}={\displaystyle \frac{V_{dc}}{2}}-u_{ao}={\displaystyle \frac{V_{dc}}{2}}\left[1-m_a\cos \left(\omega t\right)\right]\\ u_{na}={\displaystyle \frac{V_{dc}}{2}}+u_{ao}={\displaystyle \frac{V_{dc}}{2}}\left[1+m_a\cos \left(\omega t\right)\right]\end{array}\right.$

According to the NLM principle, the number of inserted SMs N_pa and N_na in the upper and lower arms are

(5)$\left\{\begin{array}{l}{N}_{pa}={\displaystyle \frac{N}{2}}-\mathrm{round}\left({\displaystyle \frac{u_{ao}}{V_C}}\right)\\ N_{na}={\displaystyle \frac{N}{2}}+\mathrm{round}\left({\displaystyle \frac{u_{ao}}{V_C}}\right)\end{array}\right.$

where V_c = V_dc/N, which represents the nominal voltage of SM capacitor.

From Equation (5), the output step voltage of the upper and lower arms u_{pa_step}, u_{na_step}, and the output step voltage of the ac side u_{ao_step} can be expressed as

(6)$\left\{\begin{array}{l}{u}_{pa\_step}=V_{dc}\mathrm{round}\left\{{\displaystyle \frac{N}{2}}\left[1-m_a\cos \left(\omega t\right)\right]\right\}\\ u_{na\_step}=V_{dc}\mathrm{round}\left\{{\displaystyle \frac{N}{2}}\left[1+m_a\cos \left(\omega t\right)\right]\right\}\end{array}\right.$

(7)$u_{ao\_step}={\displaystyle \frac{V_C}{2}}\mathrm{round}\left[N{m}_a\cos \left(\omega t\right)\right]$

3. The Capacitance Monitoring Method

3.1. Inserted Window Recognition Method

According to the equivalent circuit model of the capacitor in Figure 1, the capacitor voltage variation can be expressed as

(8)$\mathsf{\Delta }{v}_{cap}(t)=v_{cap}(t)-v_{cap}(t_0)={\displaystyle \frac{1}{C}}{\displaystyle {\int }_{t_0}^t{i}_{cap}(t)dt}+\mathrm{ESR}\cdot [i_{cap}(t)-i_{cap}(t_0)]$

where v_cap is the capacitor voltage of the SM, i_cap is the capacitor current, and t₀ is the initial time instant.

Considering the operation characteristics of MMCs and Equation (2), Equation (8) can be rewritten as

(9)$\mathsf{\Delta }{v}_{cap}(t)=v_{cap}(t)-v_{cap}(t_0)={\displaystyle \frac{1}{C}}{\displaystyle {\int }_{t_0}^t{S}_i\cdot i_{arm}(t)dt}+\mathrm{ESR}\cdot S_i[i_{arm}(t)-i_{arm}(t_0)]$

where S_i is the switching function of the corresponding SM, and i_arm is the arm current of the SM.

The period during which SM is inserted is defined as the “inserted window”. Within this inserted window, the capacitor current can be substituted with the arm current, which is accessible through arm current sensors. Traditional methods obtain switching signals from the FPGA controller, which imposes high demands on the controller. In contrast, this paper proposes a method to accurately detect the inserted window using the capacitor voltage waveforms captured by the SM voltage sensor. The principle is illustrated in Figure 3 and explained as follows:

The capacitor voltage variation ∆v_cap within one inserted window can be split into two components: ∆v_cap,r, which represents the value generated by the ESR, and ∆v_cap,c, which represents the value generated by the ESC:

(10)$\mathsf{\Delta }{v}_{cap}=\mathsf{\Delta }{v}_{cap,r}+\mathsf{\Delta }{v}_{cap,c}.$

Thus, the voltage difference between each sampling period serves as a means to determine whether the SM capacitor is inserted or bypassed. Meanwhile, ∆v_cap,r introduces a bias to recognize the specific inserted period. The bias will be dealt with in the following part.

During each sampling period, ∆v_cap is calculated from the capacitor voltage sensors. If the absolute value of ∆v_cap equals 0, it indicates that the SM is at OFF-state. Conversely, if ∆v_cap is non-zero, it suggests that the capacitor voltage is either rising or falling, indicating that the SM is at ON-state. In practical application, it is essential to set a small voltage difference threshold (v_thre) due to the impact of sampling errors and disturbances. The exact value of v_thre is subject to adjustment of different sampling frequencies (f_s). A higher f_s requires a smaller v_thre to ensure the accurate recognition of the inserted window. Otherwise, the inserted window will not be recognized properly.

The moment when capacitor voltage commences to change (or stabilize) is recognized as the start (or the end) point of the inserted window. The time interval from the start point to the endpoint is defined as an inserted window.

3.2. Discussion for Start/End Points

However, under practical operating conditions, recognizing start/end points becomes more complicated, demanding further discussion. As shown in Figure 4, the transition points of the SM operating state are located between t₂, t₃, and t₃, t₄. This is because the f_s of the voltage sensor is not high enough to capture precise timing. Consequently, simply selecting the preceding or succeeding adjacent sampling points may result in OFF-state periods being included within the inserted window. For example, in Figure 4a as an example, the switching function S_i for this specific period is as follows:

(11)$S_i=\left\{\begin{array}{l}0, T_1\le t<t^{\prime }\\ 1, t^{\prime }\le t<t^{″}\\ 0, t_1^{″}\le t<T_2\end{array}\right.$

the current–voltage relationship on the capacitor is:

(12)$\mathsf{\Delta }{v}_{cap}\left(t\right)=v_{cap}(T_2)-v_{cap}(T_1)={\displaystyle \frac{1}{C}}{\displaystyle {\int }_{t^{\prime }}^{t^{″}}{i}_{arm}(t)dt}+\mathrm{ESR}\cdot [i_{arm}(t^{″})-i_{arm}(t^{\prime })].$

This paper proposes the inserted window recognition (IWR) method based on the rules mentioned above. To guarantee that the OFF-states are excluded, rules for determining start/end points, respectively, along with the complete recognition procedure, are formulated as follows:

1. Define the capacitor voltage at three adjacent moments t_i−1, t_i and t_i+1 as v_cap(t_i−1), v_cap(t_i) and v_cap(t_i+1), as shown in Figure 5. Given that capacitor voltage either rises or falls at different charging/discharging states, their relationship adheres to the following equation with absolute values:

(13)$\left\{\begin{array}{l}\left|v_{cap}\left(t_{i-1}\right)-v_{cap}\left(t_i\right)\right|<v_{thre}\\ \left|v_{cap}\left(t_i\right)-v_{cap}\left(t_{i+1}\right)\right|\ge v_{thre}\end{array}\right..$

Showing that at (t_i, t_i+1), the SM undergoes a transition from the OFF-state to the ON-state. Set t_i+1 as the start point.

• 2.. Keep sampling until the absolute value fails to exceed the threshold.

• 3.. Define the capacitance voltage at three adjacent moments t_i+n+2, t_i+n+3 and t_i+n+4 (n = 0, 1, 2, 3…) as v_cap(t_i+n+2), v_cap(t_i+n+3), and v_cap(t_i+n+4). Their relationship satisfies the following equation:

(14) $\left\{\begin{array}{l}\left|v_{cap}\left(t_{i+n+2}\right)-v_{cap}\left(t_{i+n+3}\right)\right|\ge v_{thre}\\ \left|v_{cap}\left(t_{i+n+3}\right)-v_{cap}\left(t_{i+n+4}\right)\right|<v_{thre}\end{array}\right.$

Showing that at (t_i+n+2, t_i+n+3), the SM undergoes a transition from the ON-state to the OFF-state. Set t_i+n+2 as the endpoint.

• 4.. Denote the time interval (t_i+1, t_i+n+2) as the inserted window.

• 5.. Calculate the SM capacitor ESC_i. Set the ith inserted window of the capacitor voltage in the time interval during t_i+1 and t_i+n+2 as ∆v_cap,n. The total capacitor charge Q_cap,n is calculated by integrating the corresponding arm current i_arm over the time interval t_i+1 to t_i+n+2, in which way the ith real-time capacitance of the SM capacitor ESC_i can be derived in the ith inserted window as follows:

(15) $\mathsf{\Delta }{v}_{cap,i}=v_{cap}\left(t_{i+1}\right)-v_{cap}\left(t_{i+n+2}\right).$

(16) $Q_{cap,i}={\displaystyle {\int }_{t_{i+1}}^{t_{i+n+2}}{i}_{arm}dt}$

(17) $ES{C}_i=Q_{cap,i}/\mathsf{\Delta }{v}_{cap,i}$

Following the aforementioned steps, although the inserted window does not precisely coincide with the switching signal, it ensures that all inserted windows remain in the ON-state, even at low f_s.

To be noted, for MPPF-Cap, the ESR is very small and can be considered negligible. In contrast, for Al-Cap, the ESR is relatively large and cannot be ignored. However, since the inserted windows exclude the transition moments between the ON-state and OFF-state, the calculation only covers a period of time after insertion is completed. Therefore, the large ESR of Al-Cap does not affect the accuracy of the proposed method. Consequently, the proposed method is applicable to both MPPF-Cap and Al-Cap.

3.3. Time-Slicing Algorithm (TS Algorithm)

Figure 6 illustrates an example of how inserted windows are extracted from the capacitor voltage waveforms. The left figure shows the capacitor voltage waveforms of one SM. The figure clearly shows that the capacitor voltage has two states: charged/discharged (changed) and bypassed (unchanged). Following steps 1–5 in Section 3.2, several inserted windows can be recognized within a fundamental cycle which is marked with dashed red boxes. In contrast, the right figure displays the recognized inserted windows. The gray squares represent the recognized inserted windows, with their length corresponding to the inserted duration of each window. It can be seen that the length varies significantly.

This is due to the characteristics of the NLM, which operates at a low switching frequency, resulting in long inserted windows. This can be detrimental to capacitance monitoring, as the corresponding disturbances or measurement errors can accumulate, ultimately leading to a serious degradation in accuracy.

In order to avoid this situation, this paper proposes a time-slicing (TS) algorithm. First, a suitable time duration threshold t_thre is set. The algorithm calculates the duration during the IWR process. As shown in Figure 7, when the duration exceeds t_thre, the inserted window is sliced, and the next moment will be taken as the start point of the subsequently inserted window. The algorithm guarantees that excessively long inserted windows will not exist, thereby improving accuracy.

In summary, the features and advantages of the TS algorithm proposed in this paper are as follows:

• Error analysis: The TS algorithm not only adheres to the basic principle of the IWR method but also reduces errors.

As discussed earlier, the inserted window does not directly correspond to the switching signal; rather, it represents a period when the SM is at ON-state. Although the TS algorithm causes the inserted window to differ from the actual switching signal, it remains aligned with the core calculation principle. Furthermore, by slicing the inserted window, the accumulation of errors is minimized, thereby enhancing accuracy.

• Computational load analysis: While the TS algorithm may slightly increase the computational load, this increase can be controlled within an acceptable range.

With the algorithm, the capacitance, which was originally calculated once per inserted window, now needs to be computed three or four additional times. However, since the NLM typically results in only a few inserted windows being recognized in the single fundamental cycle, the additional computational load introduced by the TS algorithm is acceptable.

Figure 8 illustrates the overall implementation of the proposed method, which combines the IWR and TS methods. The process begins with the determination of the sensor f_s and the monitoring cycle T_m. Real-time capacitor voltage and arm current are then measured. Next, the inserted window of the capacitor voltage waveform is recognized, including its initial and endpoints. The TS algorithm is applied to improve the accuracy by appropriately slicing the inserted windows. The ESC_i is calculated based on ∆v_cap,i and Q_cap,i. This process is repeated for each subsequent window to obtain the next ESC_i+1. By averaging all the ESCs within a single T_m, the final estimated capacitance C_fin is obtained, as described by Equation (18). Finally, the method is the end of this cycle. Besides, in order to provide an intuitive measure of accuracy, the absolute error of C_fin denoted as error_cap, is introduced, as calculated by Equation (19).

(18)$C_{fin}={\displaystyle \frac{{\displaystyle \sum _{i=1}^{k}ES{C}_i}}{k}}$

(19)$erro{r}_{cap}={\displaystyle \frac{\left|C_{fin}-C\right|}{C}}\times 100\%$

where k represents the total amount of calculated inserted windows, ESC_i is the calculated capacitance of the inserted window, and C is the rated capacitance of the SM capacitor.

Since the extracted arm current signals are discrete signals, the actual formula of Equation (16) is shown below:

(20)$Q_{cap,i}={\displaystyle \sum _{a=1}^{n+1}\frac{i_{arm}\left(t_{i+a+1}\right)+i_{arm}\left(t_{i+a}\right)}{2\cdot f_s}}$

To balance the accuracy and the count of calculated inserted windows, this article sets t_thre for the TS algorithm as 300 μs. Figure 9 depicts the relationship between the capacitor errors and the inserted time duration. Red dotted line represents the trend of errors. It is notable that the errors increase gradually with the inserted time duration. When the inserted duration is less than 600 μs, the error is less than 1%. However, if 600 μs were used as t_thre, the number of sliced inserted windows would be small. Additionally, since the switching frequency is low, the total number of sliced inserted windows would not be adequate for calculation. Therefore, 300 μs is selected to ensure both a sufficient number and minimized computational error. It is worth noting that this value is not fixed and can be adjusted according to specific operating conditions of the MMC system. Influencing factors include sampling frequency, system frequency, etc.

As for v_thre, it is determined based on the sensors’ f_s and accuracy. For sensors with low f_s (10–50 kHz), within a certain range, a larger v_thre results in smaller errors. This is because, as the f_s decreases, the time interval between adjacent sampling points increases, which in turn increases the corresponding ∆v_cap. If v_thre is set small, disturbances or sampling errors may be recognized as the inserted state, leading to computational inaccuracies. Therefore, the proposed method retains high accuracy under suboptimal monitoring conditions, a smaller v_thre should be chosen. However, due to the limitations in the sampling accuracy of sensors, it is not feasible to choose a v_thre that is too small; otherwise, it will increase the cost. Based on the commonly used sensors in the MMC system with [25,31], this paper selects 0.5 V as the capacitive voltage threshold.

4. Simulation Results

To validate the proposed method, a 7.2 kV/1.2 MVA, three-phase, seven-level MMC simulation model is established in the MATLAB/Simulink. The detailed simulation parameters are provided in Table 2. v_thre of the capacitor is 0.5 V, T_m equals the system’s fundamental cycle 0.02 s, and f_s of the capacitor voltage and arm current ranges from 10 kHz to 250 kHz.

Figure 10 displays the performance of MMC, including the output voltage, output current, capacitor voltage, and arm current. The modulation index m_a is 0.8. The figure demonstrates that the simulation platform operates steadily, providing a fundamental platform for simulation verification of the proposed method.

Figure 11 illustrates a comparison between the actual switching signals and the recognized inserted windows with f_s of 100 kHz. The upper waveform represents the actual switching signal measured directly from the controller, while the lower waveform displays the recognized inserted windows based on the proposed IWR+TS method. The figure shows that for the switching signal with a short inserted duration, the recognized inserted window generally matches the switching signal. However, upon the zoom-in diagram, minor biases between them can be observed. For the switching signal with a long inserted duration, the recognized inserted window is sliced but still remains fully contained within the actual switching signal.

Table 3 compares the calculated results with and without the TS algorithm. Under the monitoring condition with f_s of 100 kHz, the capacitor voltage and the arm current are extracted. On the left side of the table, capacitance is calculated based on the entire time duration of a long switching signal. On the right side, the switching signal is first sliced using the TS algorithm before the calculation. The results indicate that the left side exhibits a larger error compared to the right side, validating that the TS algorithm improves accuracy.

Figure 12 illustrates the results of SM capacitance and its corresponding error at f_s of 100 kHz and a m_a of 1.0. The capacitance of all SMs is calculated for the inserted window over six T_m. Figure 12a,b, the monitored capacitance ranges from 499 μF to 501 μF, with errors of less than ±0.1%. Figure 12c presents the errors for each T_m in 0.02s, with the errors further reduced to as low as ±0.05%. Thus, the result reveals the feasibility of the proposed method, which achieves high accuracy.

Figure 13 studies the impact of different f_s and m_a on the accuracy of the proposed method. f_s is from 10 kHz to 250 kHz, and m_a is from 0.4 to 1.0. The results validate that with the IWR + TS method, capacitance errors remain below 0.5%. Also, as shown in the Figure, high frequency holds high accuracy.

To verify the dynamic performance of the proposed method, simulations were conducted at f_s 100 kHz and m_a 1.0, with the SM capacitance changing from 500 μF to 400 μF at t₀ = 0.4 s and from 400 μF to 500 μF at t₁ = 0.8 s. The red solid line and blue dots in Figure 14 represent the actual and calculated capacitance values with the proposed method, respectively. From the zoom-in diagram, it can be found that the calculated capacitance remains within the range of 500 μF and 501 μF before t₀. During the sudden change in capacitance at t₀, the monitored value is adjusted and stabilizes between 399 μF and 400 μF. The monitored capacitance before and after t₀ has errors less than 0.5%, and the response time to the sudden change is less than one T_m. Thus, Figure 14 demonstrates the proposed method has strong dynamic tracking capability, with a response time of less than 0.02 s and errors below 0.5%.

5. Experimental Results

To further validate the effectiveness of the proposed method, this study constructs a hardware-in-the-loop (HIL) experimental platform for a single-phase seven-level MMC system, as shown in Figure 15. HIL is a commonly used experimental platform to verify proposed methods or algorithms [19,30]. The specific parameters are listed in Table 2. A multi-functional controller board with a DSP + FPGA structure is developed to implement the MMC control method. The DSP (TI TMS320F28379D, manufactored by Texas Instruments, Dallas, TX, USA) generates the modulation wave, while the FPGA (ALTERA Cyclone IV EP4CE40F29C8N, manufactored by Intel, San Jose, CA, USA) receives the signals from the DSP and outputs the switching signals. The main circuit of the MMC system is constructed in the RT_Box simulator, with control signals provided by the FPGA. A data acquisition device (DAQ, Smacq USB-5311, manufactured by Smacq, Beijing, China) captures sensor signals with f_s from 10 kHz to 250 kHz.

Figure 16 illustrates the testing waveforms of the MMC with the NLM control method, including load voltage, load current, capacitor voltage, and arm current. The waveforms were collected from the analog output module of the real-time simulator Rt_Box. Because of the ±10 V range limitation of this module, a signal scaling module was added to Plecs. The scaled waveforms are displayed on the oscilloscope. In order to visualize the size of the waveforms, the pictures captured by the scope are labeled by the actual value. The tested output frequency is 50 Hz, and m_a is 0.8. Figure 16 shows the MMC operating waveforms, with seven output voltage levels and clean load current. The capacitor voltage varies from 1160 V to 1250 V, remaining within ±10% of the rated capacitor voltage. Thus, Figure 16 demonstrates the established MMC HIL testing platform operates effectively and can be used to evaluate the performance of the proposed method.

Figure 17 presents monitored capacitance results when the proposed IWR+TS method is applied. Figure 17a,b show the instantaneous errors and ESCs, while (c) illustrates the error_cap for each T_m. The results in (a) and (b) reveal that errors for each inserted windows are less than ±3%, with calculated capacitances ranging from 485 μF to 515 μF. This validates that the method can be used in experimental platforms. As shown in Figure 17c, although the experimental errors are larger than those observed in the simulation, the monitoring accuracy remains high after averaging, with errors reduced to below 0.5%.

Figure 18 evaluates the accuracy of the proposed method under different working conditions. The f_s is tested from 10 kHz to 250 kHz, and m_a is from 0.4 to 1.0. The bars represent the averaged capacitance over one T_m, while the blue dots are the errors of calculated results. The results show that the proposed IWR + TS method performs well across all the tested conditions. A higher f_s of voltage and current sensors leads to improved accuracy. However, the errors remain small even at 10 kHz, staying below 0.5%. An f_s of 50 kHz and 100 kHz are recommended for optimal accuracy.

Figure 19 illustrates the performance of the proposed method across all six SMs in one arm. The error_cap is calculated for f_s of 10 kHz, 50 kHz, and 250 kHz, and m_a of 0.8 and 0.4. As shown in the figure, the error_cap of each SM keeps small, all below 0.5%. Thus, the results demonstrate that the method can be easily extended to all SMs with high accuracy.

In Table 4, compared to other existing methods, the proposed approach not only eliminates the need for additional sensors, specific operation conditions, and switching signals from the FPGA but also demonstrates excellent performance on accuracy as well as easy-implementation features.

6. Conclusions

This paper proposes a novel capacitor monitoring method for MMC SMs without requiring special operating conditions or additional hardware. By fully utilizing the inherent sensor information, this article employs an IWR method to estimate the SM capacitance. Then, the TS algorithm is developed to further increase the monitoring accuracy. The impact of sampling frequency on the monitoring accuracy is also analyzed. Validated by both the simulation and experimental results, the proposed method achieves: (1) high accuracy (with errors below 0.5%) in capacitance estimation for all SM capacitors, without complex parameter estimation process, (2) minimal error even at low sampling frequencies, such as 10~25 kHz, and (3) fast and robust dynamic tracking capability applicable to all SMs. In summary, this paper provides an effective approach for monitoring the capacitance of all SMs in an entire MMC system.

Author Contributions

Methodology, W.L. and J.P.; Validation, W.L.; Formal analysis, W.L.; Investigation, W.L.; Writing—original draft, W.L.; Writing—review & editing, W.L. and J.P.; Supervision, J.P.; project administration, J.P.; funding acquisition, J.P. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

The original contributions presented in the study are included in the article material, further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflict of interest.

Footnotes

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Figures and Tables

Figure 1. A three-phase MMC converter, SM topology, and capacitor equivalent model.

Figure 2. Principle of nearest level modulation.

Figure 3. The capacitor voltage variation when the SM switches between the ON states and OFF states.

Figure 4. Inserted window recognition method. (a) Capacitor voltage, (b) inserted window when choosing the preceding point, and (c) Inserted window when choosing the succeeding point.

Figure 5. Proposed IWR method. (a) Inserted window when SMs charged, and (b) inserted window when SMs discharged.

Figure 6. Recognition of inserted windows based on capacitor voltage ripple.

Figure 7. Time-slicing algorithm.

Figure 8. Flowchart of the proposed capacitance monitoring method.

Figure 9. Relationship between calculated errors of inserted windows and inserted durations.

Figure 10. Simulation results of a three-phase MMC: (a) output voltage, (b) output current, (c) capacitor voltage of the upper arm, and (d) arm current of the upper arm.

Figure 11. Comparison between switching signal and recognized inserted windows: (a) overall figure, and (b) zoom-in diagram.

Figure 12. Simulation results: (a) calculated errors for each inserted window, (b) calculated ESCs for each inserted window, and (c) Cfin and its error for each Tm.

Figure 13. Comparison of errorcap at different fs and ma.

Figure 14. Dynamic testing of the proposed IWR + STS method.

Figure 15. MMC HIL experimental platform based on FPGA+DSP.

Figure 16. Experimental output waves of MMC (load current, load voltage, SM capacitor voltage, and arm current).

Figure 17. Experimental results: (a) calculated errors for each inserted window, (b) calculated ESCs for each inserted window, and (c) Cfin and its error for each Tm.

Figure 18. Calculated results at different fs and ma.

Figure 19. Errorcap of different SMs.

Table 1

Distribution of failures in power converter systems.

Fault Component	Fault Probability
Capacitor	30%
PCB	26%
Semiconductor	21%
Solder joint	13%
Connector	3%
Others	7%

Table 2

System parameters.

Parameters	Values
DC-link voltage	7.2 kV
Number of SMs per arm	6
Load frequency	50 Hz
Nominal SM capacitance	500 μF
Arm inductance	1 mH
Arm resistance	$0.1 \mathsf{\Omega }$
Load inductance	5 mH
Load resistance	$15 \mathsf{\Omega }$
Rated load voltage peak	3.6 kV
Rated load current peak	240 A

Table 3

Comparison of calculated results with and without the TS algorithm.

Without TS Algorithm		With TS Algorithm
		No.	Inserted Duration	ESC	Error
Inserted duration	1735 μs	1	300 μs	500.25 μF	0.059%
ESC	519.28 μF	2	300 μs	499.95 μF	−0.061%
		3	300 μs	500.28 μF	0.056%
Error	3.856%	4	300 μs	500.38 μF	0.076%
		5	135 μs	499.77 μF	−0.047%

Table 4

Comparison of different capacitance monitoring methods.

Item	Reference	AdditionalSensor	Specific Operation Condition	ComputationComplexity	Accuracy	Modulation Method
Methods require switching signals from controller	[15]	No	Withoutcurrent suppression	Medium	<2.5%	PWM
	[16,17,19]	No	No	High	<1%	PWM
	[18,20]	No	No	High	<3%	NLM
	[21]	No	No	Medium	<1%	-
	[22]	No	No	Low	-	NLM
	[23]	No	No	Low	<2%	PWM
	[24]	No	No	Medium	<1%	PWM
Methods do not need switching signals	[13,14]	Yes	No	Low	<0.85%	-
	[25]	No	Start-up process	Low	<1%	-
	[26]	No	No	High	<2%	NLM
	[27]	No	No	High	<1%	PWM
	[28]	No	No	Medium	<3.7%	PWM
	[29]	No	No	High	<1%	PWM
	[30,31]	No	Bypass SMs	Medium	<0.5%	-
The proposed method		No	No	Low	<0.5%	NLM

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