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The rapid growth of applications such as 5G, machine learning (ML), and the Internet of Things (IoT) has heightened the demand for architectures that deliver both high computational efficiency and programmability. Traditional processors struggle to meet the increasing requirements for throughput and energy efficiency, while application-specific integrated circuits (ASICs) lack the flexibility to evolve alongside changing standards. Reconfigurable architectures, particularly coarse-grained reconfigurable architectures (CGRAs), present a compelling solution by offering flexibility and dynamic programmability, coupled with nearASIC performance. However, designing reconfigurable architectures that strike an optimal balance between programmability and performance remains a costly and time-intensive endeavor. It requires the integration of application analysis, hardware design, and software development. This underscores the need for advanced design automation tools to reduce prototyping time and development costs. Despite the potential of dynamically programmable reconfigurable architectures, design automation in this space remains largely under-explored. Current solutions tend to focus either on specialized, rigid architectures optimized for performance or on flexible, generic architectures that compromise efficiency for programmability. This dissertation introduces CADA (Configurable Architecture Design Automation), a framework that automates the design of reconfigurable architectures by co-optimizing hardware and software through domain-specific design space exploration. CADA takes domain programs written in C/C++ and generates hardware-software co-designs tailored to the specification of the targeted application domain. It supports multi-size, multi-program dynamic programmability, enabling scalable, cycle-level dynamic scheduling for domain-specific programs with varying computational resource demands. The CADA pattern mapping flow significantly accelerates the compilation process, achieving a speedup of 11-70 times over existing ILP-based CGRA compilers for small to medium-sized programs (fewer than 100 nodes). For large programs (over 200 nodes), it maintains near-linear scalability in compilation time, with processing speeds of under 2 milliseconds per node. In evaluations using linear algebra benchmarks, CADA-generated designs demonstrated a 4.9× improvement in energy efficiency (GOPS/mW) and a 6.5× improvement in area efficiency (GOPS/mm2) compared to generic CGRA designs. Furthermore, CADA reduced programming latency by achieving 1.4× (Ops/Cycle) and improved reconfiguration efficiency by 10× (Ops/Bit). When targeting convolutional networks application domains, the 16-bit CADA system, synthesized using TSMC 16nm technology, achieved energy efficiency ranging from 0.4× to 23× and area efficiency from 1× to 16× compared to existing ASICs and reconfigurable architectures. The compute array achieved an average performance of 3,420 GOPS/mm2 and 22.5 GOPS/mW across multi-size convolution kernels.