An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation

Abstract

The timing jitter of a single-photon avalanche diode (SPAD) plays a critical role in the design and optimization of front-end circuits. This paper proposes a simplified timing jitter model based on Verilog-A. This model uses random numbers to determine the locations of photon absorptions and carrier avalanches based on absorption and avalanche probabilities, thereby achieving a calculation of the response time. By introducing photon detection probability, the model has corrected the response time obtained under ideal assumptions and achieved compatibility with excess bias voltage effects, which can describe the Gaussian peak of the timing jitter concisely and effectively. The simulation results are in good agreement with the measurement results, demonstrating the advantages of this model in terms of accuracy, flexibility, and adaptability. The model provides support for the collaborative optimization of the design of SPAD devices and circuits.

1. Introduction

The single-photon avalanche diode (SPAD), also known as the Geiger-mode avalanche photo diode (Geiger-mode APD), has been a significant driver of advancements in fields such as LiDAR, quantum communication, biological fluorescence detection, autonomous driving, etc. [1,2,3], due to its excellent detection sensitivity, outstanding timing resolution, low cost, and high reliability [4,5,6].

Timing jitter refers to the uncertainty in the response time seen during the photon detection process in a SPAD, and it is typically quantified by the full width at half maximum (FWHM) of the timing histogram [5]. Timing jitter is one of the key parameters that affect the phase margin and timing constraints of SPAD circuit designs, especially in high-precision time measurement and high-speed signal processing applications. In order to accurately evaluate the impact of timing jitter on circuit performance and provide a basis for circuit design and performance optimization, there is an urgent need to develop an effective SPAD timing jitter model which must be compatible with mainstream commercial circuit simulation tools such as Cadence Spectre and Synopsys HSPICE [5,6,7].

The avalanche multiplication process in SPAD exhibits a high degree of randomness, which significantly increases the complexity of developing an accurate timing jitter model. Currently, advanced predictions of timing jitters primarily rely on Monte Carlo simulations. Shiyu Xie et al. [8] developed a 3D Simple Monte Carlo Statistical Model that includes an ionization coefficient and avalanche gain calculations, takes into account the influence of the doping concentration, and is capable of predicting a device’s timing jitter. Rémi Helleboid et al. [9] proposed an electron transport and avalanche simulation method based on the Fokker–Planck viewpoint on the advection diffusion equation, which achieves the simultaneous calculation of carrier transport and collisional ionization, greatly reducing computational consumption and achieving extremely high accuracy. Yang Liu et al. [10] proposed a model that combines one-dimensional avalanche accumulation and two-dimensional avalanche diffusion, which reduces the consumption of computational resources by simulating the avalanche propagation process in segments. However, these methods based on Monte Carlo require the simulation and statistical analysis of a large number of charge carriers. Their high computational and time costs limit their application in large-scale SPADs and circuit design [8,9,10,11].

In previous studies, many researchers have modeled timing jitter based on statistical regularities. Feiyang Sun et al. [12], from another perspective, used analytical statistical methods to solve the two-dimensional avalanche current equation to model a Gaussian peak timing jitter. Rémi Helleboid et al. [13] developed a high-precision simulation by modeling the carrier’s trajectory, avalanche breakdown probability, and charge transport using a one-dimensional model of the electric field lines, which also ensures compatibility with Technology Computer Aided Design (TCAD) software. Kaveh Eyvazi et al. [14] proposed an analytical model of timing jitter for characterizing the avalanche multiplication rate of SPADs based on Fourier series, which demonstrates superior accuracy compared to traditional numerical models. However, despite these models making significant analytical and numerical advancements, they generally require solving complex differential equations and lack compatibility with commercial circuit simulators. Therefore, developing a timing jitter model that maintains accuracy, reduces computational burden, and is compatible with commercial circuit simulators has become a focal point of current research [5,6,12,13,14].

In this paper, we propose a simplified SPAD timing jitter model in Verilog-A HDL based on the SPAD avalanche principle and previous SPAD models, which can seamlessly adapt to mainstream commercial circuit simulators. To achieve efficient SPAD response time estimations, this paper constructs a simplified one-dimensional absorption–multiplication model by utilizing the distribution of absorption and avalanche probabilities and employing random numbers to determine key photon absorption and avalanche locations. This approach circumvents the need for the extensive simulation of carriers, as in Monte Carlo methods, and the complex calculations used for solving differential equations in numerical models. Furthermore, the influence of the excess bias voltage is incorporated into the model to ensure its accuracy under different working conditions. The model shows good agreement with experimental data and provides powerful support for the collaborative optimization of SPAD devices and circuits.

2. Simplified Timing Jitter Model

2.1. The Structure and Principle of SPAD

A SPAD is essentially a special p-n junction that operates using an avalanche multiplication mechanism. When the bias voltage is higher than the reverse breakdown voltage, the SPAD works in Geiger mode; otherwise, it works in linear mode. Although a SPAD can achieve significant gain through the avalanche multiplication process when in Geiger mode, there are huge safety risks. When an avalanche event happens in a SPAD, the process will persist, without external intervention, until the device is destroyed. Therefore, once the SPAD enters avalanche, it is necessary to actively lower the voltage across the SPAD using circuits to force it into linear mode, making the electric field strength insufficient to sustain the carrier’s avalanche ionization process [5,6].

In order to further improve detection efficiency, mainstream designs usually optimize device performance by separating the absorption and avalanche processes. By optimizing the depletion region, a structure with a high-electric-field multiplication region and a low-electric-field absorption region as its core is formed [5,12,15], as shown in Figure 1.

After the photons are absorbed in the absorption region, they are converted into electron–hole pairs. These carriers are subsequently injected into the multiplication region under the influence of the built-in electric field. Within the multiplication region, the carriers are accelerated by the strong electric field, causing them to undergo frequent collisions with the lattice, leading to avalanche multiplication. The carriers then exit the multiplication region and enter the neutral region, and are eventually collected by the electrodes.

During this process, when the carriers that trigger the avalanche event originate from the depletion region, the response time is relatively short, and it follows a typical Gaussian distribution [16,17]. However, when the avalanche event is triggered by carriers diffusing from the neutral region into the depletion region, there is a longer time delay and an exponential tail characteristic appears [16,17], as shown in Figure 2.

2.2. Modeling of Response Time

Since the carriers’ lifetime is much longer than the response time [18], the effects of carrier recombination are neglected. Furthermore, to make the model simple enough to run on circuit simulations and avoid the need for precise calculations of a large number of carriers, the following assumptions are made:

1. Only the absorption region is capable of absorbing photons.

2. The quantum efficiency of the absorption region is assumed to be 100%, meaning that each photon generates one electron–hole pair.

3. Only the multiplication region can perform avalanche multiplication, and the probability of avalanche events occurring is 100%.

4. The avalanche multiplication process is assumed to occur instantaneously within an extremely short period of time.

Based on the aforementioned assumptions, the avalanche multiplication process of a SPAD can be simplified into three stages:

1. Carriers are generated at a location in the absorption region and are injected into the multiplication region.

2. Within the multiplication region, carriers are accelerated by the strong electric field, gradually gathering momentum until they trigger the first avalanche ionization at a location.

3. Carriers continuously perform avalanche multiplication, generating a sufficiently large current and exiting the multiplication region under the influence of the built-in electric field.

Therefore, the response time $t_{response}$ is defined as

(1)$t_{response}=t_{ab}+t_{acc}+t_{ava}$

where $t_{ab}$ refers to the absorption region transit time, representing the time required for carriers to migrate from their generation point in the absorption region to the multiplication region; $t_{acc}$ refers to the momentum accumulation time, indicating the period during which carriers accumulate momentum in the multiplication region prior to the avalanche process; and $t_{ava}$ refers to the multiplication region transit time, which indicates the time required for the large number of carriers produced by the avalanche to move from the multiplication region to the neutral region.

2.2.1. Absorption Region Transit Time

The semiconductor’s ability to absorb photons exhibits exponential decay, meaning that the location at which carriers are generated follows an exponential distribution [19,20]; that is

(2)$X_{ab}\sim EXP\left({\displaystyle \frac{1}{\alpha }}\right)$

where $X_{ab}$ is the location where carriers are generated in the absorption region and $\alpha$ is the absorption coefficient of the semiconductor.

So, the absorption region transit time $t_{ab}$ is as follows:

(3)$t_{ab}={\int }_{X_{ab}}^{W_{ab}}{\displaystyle \frac{1}{v\left(x\right)}}dx$

where $W_{ab}$ is the thickness of the absorption region and $v\left(x\right)$ is the drift velocity of the carriers.

2.2.2. Momentum Accumulation Time

In the multiplication region, carriers require a period of time to accumulate sufficient momentum, even if they are generated at the location of the maximum electric field in the depletion region. However, calculating the momentum accumulation time accurately and conveniently is challenging. Fortunately, when the bias voltage exceeds 19 V, the statistical fluctuation of the momentum accumulation time stabilizes to an almost constant value, which is typically less than 10 ps [17].

(4)$FWHM\left(t_{acc}\right)\le 10\mathrm{ps}$

For most SPADs, the timing jitter is on the order of tens to hundreds of picoseconds. The value of $FWHM\left(t_{acc}\right)$ is nearly two orders of magnitude smaller than the value of $FWHM\left(t_{response}\right)$. Thus, the impact of the momentum accumulation time on the timing jitter can essentially be neglected.

2.2.3. Multiplication Region Transit Time

The probability of a carrier avalanche varies at different locations within the multiplication region. A random number conforming to the probability density is generated based on the avalanche probability distribution $P_{ava}$ and considered as the avalanche location $X_{ava}$.

According to our fourth assumption, the multiplied carriers are considered to be located at approximately the same location as the carriers that initiated the avalanche. Thus, the multiplication region transit time $t_{ava}$ is given by

(5)$t_{ava}={\int }_{X_{ava}}^{W_{ava}}{\displaystyle \frac{1}{v\left(x\right)}}dx$

where $W_{ava}$ is the thickness of the multiplication region.

2.2.4. Response Time Correction

The previous assumptions were absolutely ideal. In reality, not every photon is absorbed by the semiconductor and generates carriers, and not every carrier entering the multiplication region can trigger an avalanche event. Additionally, the time required for the avalanche to generate a sufficient number of carriers is not instantaneous. All these unideal factors make the photon detection probability (PDP), which is defined as the ratio of the number of SPAD avalanche events to the number of incident photons, less than 100%. Therefore, the PDP is used to correct the response time, and it can be calculated as follows [21,22]:

(6)$PDP=QE·P_A$

where $QE$ is quantum efficiency and $P_A$ is the avalanche probability, which is the integral of the avalanche probability distribution $P_{ava}$ in the multiplication region.

The absorption region transit time $t_{ab}$ and the multiplication region transit time $t_{ava}$ are, respectively, corrected to

(7)$\begin{array}{cc}\hfill t_{ab}^{*}& ={\displaystyle \frac{t_{ab}}{QE}}\hfill \\ \hfill t_{ava}^{*}& ={\displaystyle \frac{t_{ava}}{P_A}}\hfill \end{array}$

So, the response time $t_{response}$ is thus adjusted to

(8)$t_{response}=t_{ab}^{*}+t_{acc}+t_{ava}^{*}={\displaystyle \frac{t_{ab}}{QE}}+t_{acc}+{\displaystyle \frac{t_{ava}}{P_A}}$

and the total timing jitter of the SPAD is

(9)$jitter=FWHM\left(t_{response}\right)$

It is indeed challenging to precisely determine the quantum efficiency and avalanche probability of the SPAD. To facilitate calculations, this model makes conservative estimates; that is

(10)$t_{response}\approx {\displaystyle \frac{t_{ab}+t_{ava}}{PDP}}$

In different working environments, the PDP of a SPAD varies. According to some previous research results [12,15,16,23], the PDP generally exhibits an exponential growth relationship with the excess bias voltage $V_{ex}$, which is the difference between the bias voltage and breakdown voltage.

Based on Equation (10), it is evident that the response time or timing jitter exhibits an exponential decay relationship with the excess bias voltage $V_{ex}$ in our simplified model. This trend is consistent with previous findings [10,11,20]. Our simplified model naturally incorporates the impact of different working environments on the timing jitter, which can reflect the dynamic performance variations seen in the SPAD under different conditions.

3. Verilog-A HDL Implementation

3.1. Jitter Module

The first step of the simplified time jitter model is to obtain the photon absorption location and the location of the first avalanche collision. The location where photons are absorbed and carriers are generated $X_{ab}$ satisfies an exponential distribution with a mean of $1/\alpha$, so the system function of Verilog-A HDL is used to generate a random number:

(11)$X_{ab}=\$dist\_exponential\left(seed,{\displaystyle \frac{1}{\alpha }}\right)$

Verilog-A exhibits limited computational capabilities in handling calculus, making the direct calculation of Equation (3) particularly challenging. However, in most cases, the spatial variation of the electric field in the absorption region is relatively smooth, and the field strength is low. When high precision is not required, the electric field can be approximated as a constant. Therefore, Equation (3) can be simplified as follows:

(12)$t_{ab}\approx {\displaystyle \frac{W_{ab}-X_{ab}}{v}}$

The location of the carrier avalanche $X_{ava}$ is related to the distribution of the avalanche triggering probability in the multiplication region. Using TCAD software, the distribution of the avalanche probability $P_{ava}$ and the drift velocity $v\left(x\right)$ can be obtained. According to our third assumption, the $P_{ava}$ is scaled. Thus,

(13)$P_{ava}^{*}={\displaystyle \frac{P_{ava}}{P_A}}$

When high precision is not required, it can be approximated, based on experience, as follows [12,13,24]:

(14)$P_{ava}=1-exp\left(-{\displaystyle \frac{x-W_{ab}}{k·W_{ava}}}\right)$

where k is an empirical parameter that, to some extent, allows the avalanche probability distribution to take into account the increase in electric field strength from the absorption region to the multiplication region, as well as the distance traveled by carriers in the multiplication region due to their accumulated momentum, and, in most cases, k ≈ 0.1∼0.4 [12,13,19].

We can generate an avalanche location $X_{ava}$ that conforms to the scaled avalanche probability $P_{ava}^{*}$ by using the Verilog-A system function $\$dist\_uniform$ combined with the acceptance–rejection method [25,26]. Based on the drift velocity $v\left(x\right)$, we can calculate the integral result of Equation (5) in advance and use the lookup table method in Verilog-A to obtain the multiplication region transit time.

The final step is to correct the response time using the excess bias voltage $V_{ex}$ and photon detection probability, PDP, in accordance with Equation (7).

3.2. SPAD Circuit Simulation Model

Based on the structure of a traditional SPAD circuit simulation model, a jitter module, which is used for calculating response times, has been added. The state transition diagram of the complete SPAD circuit simulation model is shown in Figure 3. The SPAD circuit simulation model consists of a DC/AC module, a trigger module, a jitter module, a dark count rate (DCR) module, and an after-pulse (AP) module. Similar to the actual SPAD, the SPAD circuit simulation model also has two modes: Geiger and linear. When in Geiger mode, the model can be quenched and enter linear mode. In linear mode, the model can re-enter Geiger mode when the bias voltage is higher than the breakdown voltage.

Firstly, the internal parameters and signals of the model are initialized, and the DC/AC module calculates the avalanche current or breakdown current $I_{SPAD}$ and the reverse saturation current or dark current $I_s$. Then, we can determine whether the working mode of the SPAD is its linear mode or Geiger mode based on the excess bias voltage $V_{ex}$.

When the SPAD runs in linear mode, the DC/AC module calculates $I_s$ and $I_{SPAD}$ and outputs $I_s$. The trigger module, DCR module, jitter module, and AP module do not run in linear mode.

When the SPAD runs in Geiger mode, the trigger module will use $\$dist\_uniform$ to calculate a random number $n_{rand}$ that follows a uniform distribution of 0–1 when it receives a signal from a photon, DCR module, or AP module. If $n_{rand}$ is smaller than the PDP, the model enters an avalanche state, and it updates the timers of the DCR module and AP module. Then, the jitter module calculates $t_{response}$. Subsequently, the DC/AC module calculates $I_s$ and $I_{SPAD}$ and outputs $I_{SPAD}$ after a delay of $t_{response}$. Finally, the model determines the working state based on $V_{ex}$: if $V_{ex}>0$, the model maintains a self-sustaining avalanche state, returns to the DC/AC module, and outputs $I_{SPAD}$; if $V_{ex}<0$, the model is quenched. The working process of the DCR module and AP module is detailed in [6].

4. Simulation and Verification

4.1. Measurement Platform and Simulation Parameters

As shown in Figure 4 and Figure 5, a light pulse was generated by a picosecond pulse laser (PDL800D from PicoQuant in Berlin, Germany) with a typical pulse width of 20 ps; the timing jitter was recorded using a time-correlated single-photon counting system (FT1010 from Siminics in Shanghai, China); the time delay and gate signal were controlled by a digital delay/pulse generator (DG645 from Stanford Research Systems (SRS) in Sunnyvale, CA, USA); and a detachable black aluminum box was used to shield the external light environment during measurement.

The detector uses an InGaAs/InP SPAD (from Xi’an Institute of Optics and Precision Mechanics, Chinese Academy of Sciences in Xi’an, China) designed by our research group, as shown in Figure 6a. Its built-in electric field distribution was obtained through TCAD simulation during its design, as shown in Figure 6b,c. The circuit simulation platform uses Cadence Virtuoso (version: ic6.1.7-64b. 5002) and the simulator used is Spectre. The device specs of the InGaAs/InP SPAD and the parameters used in this simulation are shown in Table 1.

4.2. Results and Discussion

The response timing histograms from measurements and simulations at different excess bias voltages are shown in Figure 7, indicating that the proposed simplified SPAD time jitter model can effectively restore the Gaussian distribution curve of the time jitter and accurately estimate the FWHM. The relative error between the measurement and simulation is below 15%, as shown by the green in Figure 8. However, near the Gaussian peak, the simulation results of the response time are slightly earlier than the measurement results and there is slight distortion in the shape. This is due to our neglect of $t_{acc}$ during modeling and our fourth assumption, which states that avalanches occur instantaneously. There is also a deviation in the model at the end of the time jitter curve. This deviation is mainly due to the model not considering the formation mechanism of exponential tails.

As seen in Figure 8, both the measurement and simulation results exhibit a characteristic exponential decay of the time jitter with the increase in the excess bias voltage, which is consistent with previous findings [10,15,17,24]. The fitting for the timing jitter measurement is $jitter=352.1·e^{-0.2211·V_{ex}}$, while the fitting of the simulation is $jitter=394.0·e^{-0.2254·V_{ex}}$, which can be used for a quick estimation of the timing jitter.

The simulation results are consistently slightly larger than the measured values, primarily due to conservative adjustments made to the $t_{ab}$ and $t_{ava}$. Additionally, the model omits $t_{acc}$, which constrains the deviation of the simulation results in a fortunate manner, preventing the excessive divergence from the actual measurements that could be caused by these conservative adjustments to a certain degree.

Table 2 shows a summary of the comparison of our model with state-of-the-art SPAD jitter models. We comprehensively evaluated the models in terms of four aspects: method, error, computational consumption, and whether it is compatible with circuit simulators. It can be seen that our model performs well in precision and shows significant advantages in computational efficiency and compatibility.

5. Conclusions

In this paper, a simplified SPAD timing jitter model in Verilog-A that can be readily implemented in circuit simulators was developed. Compared to the Monte Carlo method and numerical models, this model offers significant speed advantages. The simulation results align well with actual measurements. This simplified model meets the precision requirements for a SPAD timing jitter in circuit design processes, making it highly suitable for the simulation and optimization of SPAD front-end circuits, with excellent versatility and compatibility.

Author Contributions

Conceptualization, L.X. and X.W.; methodology, L.X. and L.L.; software, L.X.; validation, Y.C., K.Q. and Z.X.; formal analysis, L.X. and L.L.; investigation, L.X., Y.C. and K.Q.; resources, Y.C. and K.Q.; data curation, Z.X.; writing—original draft preparation, L.X., L.L. and Z.X.; visualization, J.W., C.S. and T.L.; project administration, F.Y. and X.W.; funding acquisition, X.W. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

The data from the study can be made available by the corresponding author (X.W.: [email protected]) upon reasonable request.

Conflicts of Interest

The authors declare no conflicts of interest.

Abbreviations

The following abbreviations are used in this manuscript:

SPAD	Single-photon avalanche diode
APD	Avalanche photo diode
DCR	Dark count rate
AP	After-pulse
FWHM	Full width at half maximum
PDP	Photon detection probability

Footnotes

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Figures and Tables

Figure 1. Structure of absorption, grading, charge, and multiplication (SAGCM) SPAD.

Figure 2. Typical SPAD timing histogram.

Figure 3. The state transition diagram of the SPAD circuit simulation model.

Figure 4. A principle block diagram of the measurement platform.

Figure 5. Measurement platform and equipment used.

Figure 6. The InGaAs/InP SPAD used: (a) appearance; (b) built-in electric field distribution; (c) relationship between built-in electric field and position.

Figure 7. The response timing histograms of the SPAD, at a temperature of 297 K with a 1550 nm wavelength beam at a frequency of 20 kHz. The excess bias voltage in each histogram is (a) 5 V; (b) 4 V; (c) 3 V; (d) 2 V; (e) 1 V; and (f) 0.5 V.

Figure 8. The timing jitter of the SPAD vs. the excess bias voltage at a temperature of 297 K and with a 1550 nm wavelength beam with a frequency of 20 kHz.

Table 1

The device specs of the InGaAs/InP SPAD and the parameteres of the timing jitter model.

Parameter	Symbol	Value
saturation current	$I_s$	$1\times {10}^{-9}$ A
built-in voltage	$V_{bi}$	0.8 V
breakdown voltage	$V_{BD}$ or $BV$	67 V
breakdown current	$I_{SPAD}$ or $IBV$	$1\times {10}^{-4}$ A
zero-bias junction capacitance	$C_{JO}$	$1.1\times {10}^{-12}$ F
sidewall zero-bias junction capacitance	$C_{JSW}$	0 F
absorption coefficient	$\alpha$	$1.3\times {10}^5$ /cm
electron mobility	${\mu }_e$	$2\times {10}^4$ cm2/(V·s)
hole mobility	${\mu }_h$	$3\times {10}^2$ cm2/(V·s)
saturation drift velocity	$v_{sat}$	$1.5\times {10}^7$ cm/s
absorption region width	$W_{ab}$	$2\times {10}^{-4}$ cm
multiplication region width	$W_{ava}$	$1\times {10}^{-4}$ cm
absorption region electric field	$E_{ab}$	$1\times {10}^5$ V/cm
multiplication region electric field	$E_{ava}$	$4\times {10}^5$ V/cm
		25.2%@5 V, 20.7% @ 4 V,
photon detection probability	PDP	15.7%@3 V, 12.9% @ 2 V,
		10.1%@1 V, 9.4% @ 0.5 V

Table 2

Summary of comparison of our model with state-of-the-art jitter models.

Reference	Year	Method *	Error	Computational Consumption	Compatible with Circuit Simulators
[8]	2020	3D-MC	<9.7%	∼20 h (Intel x64 CPU + 32 GB RAM)	No
[13]	2022	1D Anal. + 3D Numer.	<23.5%	>20 min (32 CPUs)	No
[14]	2023	Fourier series + 2D Anal.	<16.4%	N.A.	No
[10]	2024	1D-MC + 2D Numer.	<24.1%	N.A.	No
This work	2025	1D Anal. + 1D Numer.	<14.8%	<2 min (Intel i5 8400 + 16 GB RAM)	Yes

* MC stands for Monte Carlo; Numer. stands for numerical; Anal. stands for analytical.

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