Efficiënt Computing System for Satellite Image Processing Processor

Abstract

Approximate computing plays a significant role in signal processing and image processing applications. Radix-8 approximate novel booth multiplier (R8ANBM) based on approximate novel booth encoder (ANBE) is proposed in this paper to validate approximate computing. The proposed design is synthesized and simulated in Xilinx ISE 13.2. The experimental results show that the proposed multiplier performs better in terms area, speed and energy consumption. The proposed R8ANBE reduced the number of 4 input LUTs by 23.07%, 17.94%, 19.87%, 16.66%, 13.46%, 8.33%, 12.82%, 9.61%, 12.17% and number of occupied slices by 22.33%, 30.09%, 25.24%, 29.12%, 14.56%, 17.47%, 13.59%, 12.62%, 17.47% when compared with the existing techniques such as conventional booth multiplier, R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2, R8ABM3 respectively. It achieved the accuracy as 67.3% which is higher than exisitng approximate booth multipliers. The proposed R8ANBM is applied to image sharpening applications and the performances are analyzed in terms oferror metrics such as ralative mean error distance, normalized mean error distance and peak signal to noise ratio. The above proposed system was implemented using 45nanometer technology library. With applications in low-power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics, and nanotechnology, there is an increasing interest in power minimization.

Headnote

Keywords: computing, approximate computing, accuracy, booth encoding, energy consumption

Approximate computing plays a significant role in signal processing and image processing applications. Radix-8 approximate novel booth multiplier (R8ANBM) based on approximate novel booth encoder (ANBE) is proposed in this paper to validate approximate computing. The proposed design is synthesized and simulated in Xilinx ISE 13.2. The experimental results show that the proposed multiplier performs better in terms area, speed and energy consumption. The proposed R8ANBE reduced the number of 4 input LUTs by 23.07%, 17.94%, 19.87%, 16.66%, 13.46%, 8.33%, 12.82%, 9.61%, 12.17% and number of occupied slices by 22.33%, 30.09%, 25.24%, 29.12%, 14.56%, 17.47%, 13.59%, 12.62%, 17.47% when compared with the existing techniques such as conventional booth multiplier, R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2, R8ABM3 respectively. It achieved the accuracy as 67.3% which is higher than exisitng approximate booth multipliers. The proposed R8ANBM is applied to image sharpening applications and the performances are analyzed in terms oferror metrics such as ralative mean error distance, normalized mean error distance and peak signal to noise ratio. The above proposed system was implemented using 45nanometer technology library. With applications in low-power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics, and nanotechnology, there is an increasing interest in power minimization.

Povzetek: Predstavljena je izboljsana pomnilnisko ucinkovita porazdeljena arhitektura za 2D diskretno valcno transformacijo (DWT), prilagojeno satelitskim slikam. Z uporabo stiskanja iskalne tabele (LUT) predlagana zasnova zmanjsuje pomnilniske zahteve, hkrati pa ohranja racunsko ucinkovitost, kar predstavlja pomemben prispevek k visoko zmogljivim VLSI implementacijam za obdelavo slik

1 Introduction

In this modern world, one of the recent trends in VLSI design is approximate computing which focused the tradeoff factors area, power consumption and speed. In this emerging computing method, the internal structure of the architecture is modified by eliminating certain logic gates which leads to the erroneous output for some cases. But this error is acceptable in image processing applications, data mining, filtering, digital signal processing, machine learning, computer vision, etc [1]. Due to the advantages of approximate computing [2], the researchers concentrate on different approximation approaches and utilize these approaches in certain applications. In addition to that, approximate computing plays a significant role in hardware accelerators for customization of the hardware modules and for processing large amount of data [3].

Approximate accelerators are designed in [4] by collecting the most appropriate approximate elements from libraries where lot of approximate arithmetic circuits are stored. It uses space exploration methodology for approximate circuit collection and uses machine learning techniques for estimation of computational modules. The fundamental components involved in the approximate accelerator are approximate adder and approximate multiplier. So these should be designed with low power consumption and high performance to make it well suited for effective applications. Approximate computing is also applicable for biometric security systems [5]. In this method, the runtime of the application is reduced by applying the encoding techniques to the resultant obtained from iris scanning.

Multiplier is a power-hungry arithmetic circuit used in most of the signal processing applications. To reduce the power consumption of the multiplier designs, approximate multipliers are focused by the researchers [6]. In approximate multiplication, the approximation is inserted in partial product formation or partial product reduction or partial product summation. Most of the approximation approaches uses encoding process for the partial products to reduce the complexity of the design. Then the encoded partial products are compressed with the help of approximate half adder and approximate full adder [7].

This paper proposed an approximate novel booth encoder (ANBE) for radix-8 booth multiplication. The proposed encoder reduces the number of partial products leads to the reduction in the complexity. It uses approximate half adders to generate the 3X product term thereby it facilitates the simplest method to partial product formation. The proposed radix-8 booth multiplier using ANBE is designed in Xilinx ISE 13.2 and coded in

Verilog HDL. The proposed radix-8 approximate novel booth multiplier (R8ANBM) outperforms better than existing radix-8 booth multipliers. At long last, the ftuitfulness of the proposed radix-8 booth multiplier design is demonstrated with image sharpening applications.

The remaining section of this research work is as follows. Section 2 describes the works related with booth encoders and approximate multipliers. Section 3 presents the proposed approximate novel booth encoder. It also explains the logical diagram and operation of the ANBE. Section 4 explains the proposed radix-8 approximate booth multiplier and Image sharpening using proposed booth multiplier. Performance analysis is given in Section 5 and error analysis is given in Section 6. Finally, the work is concluded in Section 7.

2 Related work

Multipliers have significant importance in image processing and signal processing applications. Honglan Jiang presented an approximate radix-8 booth multiplier based on encoding methods which is used for reducing the partial product count [8]. This approximate multiplier eliminates the complexity of conventional radix-8 booth multiplier by the exploitation approximate adder which computes the sum of IX and 2X products. This multiplier is applied in the filtering applications to evaluate the performance of the approximate radix-8 booth multiplier. The observation results showed that, there is a tradeoff between power consumption and accuracy.

Area and power efficiënt booth multiplier are designed in [9]. The adder and subtractor used in this multiplier are designed using multiplexers. The code block also fully designed by multiplexers. In this booth multiplier, there are no components other than multiplexers and it is well suited for graphics applications. V. Leon et al presented hybrid radix encoding techniques for partial product formation This hybrid approach is suitable for signed multiplier where approximate radix-4 encoding approach is used in least significant bits and accurate approach is used in most significant bits [10]. In this method the highest radix values are converted to two the power of values and it is termed as rounding. Since it achieves high energy efficiency, there is a tradeoff between energy consumption and accuracy.

8 point Fast Fourier Transform is designed using approximate radix-8 booth multiplier [11] which partially performed the operation of butterfly unit. The remaining operation of butterfly unit is performed by recoded adder and Kogge Stone adder. It utilized the approximation approaches for generating 3X product leads to low power consumption. It also uses external circuit for error detection as well as error correction leads to more area. Suganthi Venkatachalam designed three different approximate booth multipliers ABM1, ABM2 and ABM3 [12]. Here, the approximation is inserted in the booth encoding process. It reduces the logic complexity presents in the partial product formation.

This design is applied in Finite Impulse Response (FIR) filter to evaluate the performance of ABM1, ABM2 and ABM3. These are performing better in terms of area and power consumption with delay overhead.

Alberto A. Del Barrio et al designed a carry save radix-8 booth multiplier [13] that reduced the number of partial product rows into half. It uses 4:2 compressors for forming partial product matrix (PPM) and Kogge Stone adder for carry propagate addition. It increased the speed with area overhead due to the utilization of parallel prefix adder. Bayadir A. Issa et al designed a fused multiply add unit using radix-8 booth multiplier. It is represented in floating point format and so the 53x53 bit mantissa product is obtained by performing booth multiplication [14]. The partial products are reduced with the aid of 4:2 carry save adder tree which increased the speed of the whole unit. Jiang et al [15, 16] compared approximate arithmetic circuits to utilize these in the accumulation stages. High accuracy fixed width booth multipliers are designed and its error merries are analyzed in [17, 18]. Choi et al [19] designed hybrid radix truncated multiplier for mobile applications. Different booth encoding approaches, approximation techniques, booth multiplier structures are discussed [20-23] to evaluate the limitations of these approaches.

3 Proposed approximate novel booth encoder (anbe)

Let A is n-bit signed multiplicand and B is n-bit signed multiplier and these are expressed in two's complement format.

Every four bits are grouped from right to left and it is termed as a set {b_(3q+2), b_(3q+l), b_3q, b_(3q-l)}. During this group formation, the least significant bit (b_ (-1)) is assigned as zero and the most significant bit (b_(n-l)) is assigned as sign bit. Before encoding process, the multiplier bits are grouped into various sets and it is depicted in Figure 1. The encoded format for every group is represented by the following equation multipliers is multiplied with the multiplicand to get the partial products and it can be represented as follows.

where Ppq represents partial products in the mth row. For every group, the most significant bit of the encoded values is considered for sign computation. If it is zero, it is termed as positive, otherwise termed as negative. During the positive cases, 2 x multiplicand (2A) can be obtained by left shifting the A by one bit and 4 x multiplicand (4A) can be obtained by left shifting the A by two bits. 3 x multiplicand (3A) can be obtained by adding A and 2A. When the sign is negative, then two's complement is applied to get the partial product row. The logic diagram of existing R8ABE1 is shown in Figure 2.

In R8ABE1, the partial product Pppq can be computed by the following expression.

The logic equation of the existing R8ABE1 is modified to reduce the area as well as power consumption of the encoder design. The logic expression given in (5) is simplified to get the novel approximate booth encoder. The partial product bit Pppq at qth row in pth position can be expressed by the following equation

The logic diagram of the proposed ANBE is shown in Figure 3. The proposed approximate novel booth encoder reduces the area by reducing the number of logic gates. It requires 31 logic gates to complete the encoder design which is lesser than existing R8ABE1 that requires 35 logic gates. So, 4 logic gates are reduced for every partial product row. If there is y number of partial product rows, then 4y logic gates are reduced.

From Tab Ie 1, it is observed that, the proposed ANBE cannot generate the exact output in 4 cases. [Pp] _pq generate erroneous outputs when B_q=+3 and B_q=-3. In four cases, B_q=±3 is present; hence the probability of error is 4/16 as Va

4 Proposed radix-8 anbe based multiplier (r8anbm)

Three major operations of multiplier are partial product generation, reduction and addition. The additional process involved in the booth multiplier is booth encoding. Since this research focused the approximate booth multiplier, approximate booth encoder is proposed. In this proposed multiplier, the partial products are generated by approximate novel booth encoding approach. The positioning of these partial products is same as the existing booth multiplier. Then the reduction of partial products is performed by 4:2 compressors, full adder and half adder. Finally, the reduced partial products are added with the area efficiënt and high-speed Brent Kung (BK) adder.

The dot diagram of proposed radix-8 approximate novel booth multiplier is shown in Figure 4. The blue colour, red colour and green colour denotes the sign of booth encoded digits, inverted sign bit and binary one respectively. After forming these encoded products, the partial products are accumulated using compressors and

The 225x225 grey scale image is selected for quality evaluation. Image compression using different approximate booth multipliers are analyzed and output images are shown in Figure 2.

5 Performance analysis

The proposed R8ANBM multiplier and the existing multipliers are designed and simulated using Xilinx ISE 13.2 and these are coded using Verilog HDL. The performances of the proposed R8ANBM are analyzed in terms of area, delay and energy efficiency.

Area is analyzed in terms of number of 4 input LUTs, occupied slices and number of logic gates. Area of the proposed ANBE is compared with the existing booth encoding approaches and it is tabulated in Table 2. From Table 2, it is cleared that the proposed ANBE requires a smaller number of logic gates which is lesser than other existing approaches. R8ANBE has 22.58%, 12.90%, 9.67% and 12.90% less gate count than conventional booth encoding, R8ABE1, R8ABE2 and R8ABE3 respectively.

occupied slices by 22.33%, 30.09%, 25.24%, 29.12%, 14.56%, 17.47%, 13.59%, 12.62%, 17.47% when compared with the existing techniques such as conventional booth multiplier, R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2, R8ABM3 respectively.

Time consumed by the different approximate multipliers to complete the operation is expressed in the comparison chart and it is shown in Figure 4. The proposed R8ANBM has reduced the delay by 31.86%, 29.24%, 27.91%, 30.94%, 27.51%, 24.87%, 16.03%, 18.45% and 18.88% when compared with the existing techniques such as conventional booth multiplier, R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2 and R8ABM3 respectively.

Energy consumption of the approximate multiplier design is the power delay product. Energy consumption of various approximate booth multipliers are compared and it is tabulated in Table 3.

From the tabulated results, it is observed that the proposed R8ANBM reduces the energy consumption by 56.64%, 52.84%, 45.26%, 40.22%, 31.77%, 28.74%, 22.07%, 16.62% and 20.05% when compared with conventional booth multiplier, R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2 and R8ABM3. The proposed R8ANBM performs better in terms of area, speed and energy consumption.

6 Error analysis

The error fed by the approximate novel booth encoder in the proposed approximate novel booth multiplier is analyzed in terms of normalized mean error distance (NMED), mean relative error distance (MRED), accuracy and peak signal to noise ratio (PSNR). These error metrics are based on error distance which can be computed by calculating the difference between exact product and inexact product. MED is defined as the average values of error distance for all possible input combimations. NMED is the normalization of MED values [24] and it can be computed by the following expression.

Here, n denotes the bit width of multiplicand and multiplier. EDp denotes the error distance value of pth input combination Max ED denotes maximum error distance value of the outputs. MRED is defined as the mean value of the ratio of error distance to the exact output for all possible combination of inputs. It can be computed by the following expression.

Here, EO denotes the exact output at pth combination of input. The accuracy of the proposed R8ANMB is the ratio of number of exact outputs to the total number of outputs and it can be expressed as follows.

The accuracy of the design is directly proportional to the number of exact outputs. So, the accuracy is improved by increasing the number of exact outputs.

Error metrics in terms of NMED, MRED and accuracy of the proposed R8ANBM are compared with the existing approximation booth multipliers and it is tabulated in Table 4. The tabulated results showed that the proposed R8ANBM reduces the NMED by 63.03%, 34.98%, 43.09%, 60.65%, 49.65%, 40.35%, 50.13%, 61.90% and MRED by 73.46%, 76.93%, 27.66%, 69.68%, 57.08%, 24.40%, 54.46%, 47.64% when compared with R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2, R8ABM3 respectively. The proposed R8ANBM achieves better accuracy than exisiting approximate booth multipliers. The conventional accurate booth multiplier achieves 100% accuracy. The proposed R8ANBM achieved the accuracy as 67.15% which was increased by 32.41%, 38.76%, 33.01%, 3.36%, 5.82%, 17.70%, 36.39% and 11.33% when compared with R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2 and R8ABM3 respectively.

In image sharpening applications, PSNR is one of the error metrics used to evaluate the quality of the output images. PSNR is measured in decibel and it can be computed by the following expression where, max p denotes the input image's maximum pixel value and MSE denotes mean square error value of the image.

Image sharpening of radix 8 booth multipliers is tested with two different test iamges (Lena and Barbara) and its PSNR values are computed to show the effectivity of the proposed R8ANBM multiplier. From Figure 5, it is exhibited that, the proposed R8ANBM multiplier has low PSNR values compared with conventional booth multiplier and high PSNR values compared with another existing approximate booth multiplier. The proposed R8ANBM has 18.49%, 27.70%, 15.59% high PSNR for lena image and 9.87%, 21.20%, 15.57% high PSNR for barbara image compared to the existing approximate booth multipliers such as R8ABM1, R8ABM2, R8ABM3 respectively.

7 Conclusion

This paper talk about the approximate novel booth encoder design and radix-8 approximates novel booth multiplier based on ANBE. The accuracy of the proposed R8ANBM is high over other approximate booth multipliers, due to the less error probability of ANBE. Less number logic gates requirement in ANBE design leads to low area and low energy consumption in multiplier design. It also performs better in terms of NMER and MRED. The proposed R8ANBM reduces the NMED by 63.03%, 34.98%, 43.09%, 60.65%, 49.65%, 40.35%, 50.13%, 61.90% and MRED by 73.46%, 76.93%, 27.66%, 69.68%, 57.08%, 24.40%, 54.46%, 47.64% when compared with R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2, R8ABM3 respectively. The proposed R8ANBM is analyzed for image sharpening applications. It can achieve high PSNR value as 37.8 for lena image and 42.3 for barbara image. The proposed R8ANBM achieved the accuracy as 67.15% which was increased by 32.41%, 38.76%, 33.01%, 3.36%, 5.82%, 17.70%, 36.39% and 11.33% when compared with R4ABM1, RAD64, ABM1, HLR-BM1, HLR-BM2, R8ABM1, R8ABM2 and R8ABM3 respectively. The proposed system is suitable for nanotechnology applications to reduce the power effectively.

Author contributions statement

"A. Azhagu Jaisudhan Pazhani done implementation of algorithms, methodology, preparation of flow chart and manuscript, result analysis for the manuscripts."

Conflict of interest

There is no conflict of interest in this paper regarding publication

Data availability statement

The data that supports the findings of this study are available within the article.

Funding

No funding was received for this study.

References

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