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Tiny Machine Learning (TinyML) applications are rapidly expanding, which is driven by demand for real-time data processing in sectors like healthcare, brain-computer interfaces, and portable devices, requiring lightweight, energy-efficient, and responsive models. Binary Vector Symbolic Architecture (VSA), a classic brain-inspired model using high-dimensional binary vectors and bitwise operations, addresses these needs through efficient parallel processing. However, current binary VSA models face challenges due to heuristic training methods and excessively high dimensionality (i.e., around 10,000).
We address these limitations by proposing both algorithmic optimizations and hardware implementations for binary VSA, tailored to practical applications on resource-constrained devices. Regarding algorithmic optimization, we propose to transform binary VSA into a partial binary neural network (BNN). This approach effectively reduces dimensional requirements from approximately 10,000 to under 100, maintaining inference performance without additional overhead. Correspondingly, we employ other optimization strategies to expand our dimension-reduced VSA model into various applications. In the hardware implementation, we examine practical applications of binary VSA on various platforms, such as microcontroller units (MCUs) and Field Gate-Programmable Arrays (FPGAs). These implementations enhance efficiency and minimize resource consumption, enabling microsecond-level inference speeds and milliwatt-scale power usage, significantly surpassing existing TinyML frameworks based on experimental results. Moreover, we demonstrate the versatility of our binary VSA model by applying it to diverse applications under practical considerations, validating its effectiveness and efficiency in practice.