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The detection and repair of hardware bugs have become increasingly important over the past decade. In particular, security-related issues arising from these bugs have been the focus of significant academic and industrial efforts. It is crucial to detect defects in hardware as early as possible to reduce costs, efforts, and damage to reputation down the line. Existing solutions rely on design-specific information, expertise, and techniques. These constraints limit the generalizability of solutions across various digital designs, restricting automation and scalability. Additionally, security verification is inherently non-exhaustive, as some vulnerabilities only emerge when exploited by malicious actors. Another limitation of current approaches is their lack of ability to `learn' from previous issues and solutions.
This thesis provides some strategies, including Static Analysis and Generative AI, for applying bug detection and repair techniques at an earlier stage of the system-on-chip (SoC) development lifecycle - without needing a full-fledged testing framework. These strategies are employed at the register-transfer level (RTL) code by examining the structure and elements of the code, along with associated information like specifications, comments, and more general guidelines for secure code like the Common Weakness Enumerations (CWEs). The contributions include: i) improving generalizability by moving away from design-specific frameworks and implementing scanners that can identify a broad range of vulnerabilities i.e., CWEs; ii) focusing on security-related bugs to develop security aware linters and fix security bugs by using LLMs; and iii) leveraging LLMs to execute detection and repair of bugs at RTL, demonstrating how generative AI-based tools can succeed by learning from training, fine-tuning, and in-context learning.