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Analog/mixed-signal (AMS) circuits traditionally require manual design efforts by experienced engineers. This process is labor-intensive, expensive, and often lacks explainability. Recently, researchers have employed large language models (LLMs) in various fields, showing potential for automating AMS circuit design as well. However, while state-of-the-art LLMs possess significant knowledge, they are incapable of managing the entire design process alone. To address this challenge, we present a series of data-driven methods to enhance AMS circuit understanding and design automation.
We begin by addressing the multimodal LLM challenge of understanding schematics and parsing circuit topology. This limitation currently hampers the use of abundant schematics available in academic literature. We propose a schematic parsing algorithm based on advanced computer vision techniques to convert schematics directly into netlists. Initially, we train an object detection model based on YOLO to identify individual schematic elements. Subsequently, we employ an instance segmentation model based on U-net to detect wires and collect connectivity between elements to generate netlists. By processing 2,686 schematics from literature with this data transformation pipeline, we create the AMSnet dataset. To enrich its data modality, we manually annotate the schematics with functional traits and reconstruct them in OpenAccess format, making them usable in popular EDA software.
With the data support from AMSnet, we are ready to automate circuit design. We introduce AMSgen, an LLM-driven design flow that spans from performance specifications to post-layout simulation. This process begins with a series of LLM inquiries to derive a block-level design strategy, which we convert into a list of relation-label pairs. Using these pairs, we query our dataset to retrieve subcircuit blocks and assemble them into a complete circuit topology. Next, we utilize Bayesian optimization (BO) to determine circuit sizing. This algorithm intelligently selects sets of parameters and performs simulations to ascertain the corresponding performance. Through a series of trials and errors, the algorithm eventually converges on an optimal set of parameters that achieve desired performance. If performance goals remain unmet after a maximum number of trials, we revisit the topology generation step, using the actual performance as a reference to suggest alternative circuit topologies through LLM knowledge. Our method is evaluated in two case studies, where we successfully generate an operational amplifier and a comparator without human intervention. Additionally, with support from analog cells (Acell), we introduce an automated layout step within the sizing loop, ensuring that the generated circuits consider physical design aspects such as parasitic effects, thereby enhancing reliability.
A limitation of AMSgen is its reliance on BO for end-to-end simulation, which can be costly for larger circuits with more sizing parameters, as the search space grows exponentially. To extend our automated design process to larger circuits, we leverage analytical equations and propose a hierarchical design flow. Inspired by traditional engineering approaches, we first derive performance requirements for the subcircuits from the overall specifications, then optimize them independently. This significantly reduces the number of parameters we need to optimize in each loop, making the design approach more feasible. The entire process is driven by a dependency graph, ensuring that all theoretical calculations and subcircuit optimizations are conducted in order, populating each parameter before it is required. This approach is evaluated on a SAR ADC (successive approximation register analog-to-digital converter) design, enabling the production of ADCs with 12-14 bits of resolution and up to 1MHz of sampling frequency, again without human intervention.
In summary, we propose a series of methods to collect, transform, and utilize AMS circuit data in automated AMS circuit design. Our approaches allow us to design complex circuits such as SAR ADCs, comprising over 200 devices, with minimal human effort beyond the data collection step. For future work, our methods could extend to additional features such as testbench generation and further automation in data annotation to reduce human effort significantly.