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In recent years, many chaos-based encryption algorithms have been proposed. Many of these are based on established designs and populate their S-boxes with values derived from chaotic maps, following conventional implementation strategies to enable comparison with their original non-chaotic counterparts. In contrast, this work proposes a novel approach: a Chaos-Based Substitution Box (CB-SBox) implementation, in which conventional ROM-based S-boxes are replaced by a digital circuit that directly executes a selected chaotic map. This method enables the construction of S-boxes with long word lengths through an FPGA-based programmable circuit that allows for variable S-box lengths, facilitating the analysis of S-boxes of varying sizes, and ultimately enhancing security, particularly for larger S-boxes, as demonstrated by increased resistance to linear and differential cryptanalysis. Furthermore, the proposed CB-SBox achieves reductions in both area and power consumption compared to size-comparable ROM-based S-boxes. A 19-bit chaos-based S-box consumes just 0.0238% of the area and 0.0241% of the power required by an equivalent ROM-implemented S-box while providing the same level of security. The inherent unpredictability of non-linear chaotic behavior causes the proposed chaos-based S-boxes to exhibit non-bijective characteristics, making them well suited for application in non-invertible cryptographic primitives, such as hash functions and Feistel networks. The proposed CB-SBox is implemented in a Feistel network as described in the literature, and the results are provided.
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; Cruz Carlos Augusto de Moraes 2
; Saraiva Isaias Abner Lima 1
; Santos, Fávero Guilherme 3
; dos Santos Junior Carlos Raimundo Pereira 1
; Indrusiak Leandro Soares 4
; Finamore Weiler Alves 5
; Glesner Manfred 6 1 SENAI Institute of Innovation in Microelectronics (ISI-ME), National Service for Industrial Apprenticeship (SENAI/AM), Av. Gal. Rodrigo Otávio Jordão Ramos, nr. 2394, Industrial District, Manaus 69075-005, Brazil; [email protected] (I.A.L.S.); [email protected] (F.G.S.); [email protected] (C.R.P.d.S.J.), Center of R&D in Electronic Technology and Information (CETELI), Federal University of Amazonas (UFAM), Av. Gal. Rodrigo Otávio Jordão Ramos, nr. 3000, Industrial District, Manaus 69077-000, Brazil; [email protected]
2 Center of R&D in Electronic Technology and Information (CETELI), Federal University of Amazonas (UFAM), Av. Gal. Rodrigo Otávio Jordão Ramos, nr. 3000, Industrial District, Manaus 69077-000, Brazil; [email protected]
3 SENAI Institute of Innovation in Microelectronics (ISI-ME), National Service for Industrial Apprenticeship (SENAI/AM), Av. Gal. Rodrigo Otávio Jordão Ramos, nr. 2394, Industrial District, Manaus 69075-005, Brazil; [email protected] (I.A.L.S.); [email protected] (F.G.S.); [email protected] (C.R.P.d.S.J.)
4 Distributed Systems and Services Group, School of Computer Science, University of Leeds (UoL), Leeds LS2 9JT, UK; [email protected]
5 Department of Electronic and Computer Engineering, Polytechnic School, Federal University of Rio de Janeiro (UFRJ), University City, Fundão Island, Rio de Janeiro 21941-914, Brazil; [email protected]
6 Microelectronic Systems (MES) Research Group, Department of Electrical Engineering and Information Technology (etit), Technische Universitat Darmstadt, St. Merckstrasse, nr. 25, Room S3|06 343, 64283 Darmstadt, Germany; [email protected]