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As performance gains from physical scaling plateau, computer architecture optimizations are a cornerstone for future computing performance improvements. To evaluate their processor and computer system designs, engineers have traditionally strived to maximize performance metrics while minimizing power consumption and die areas. A major influence on chip design is that cutting-edge semiconductor design and manufacturing have always been a tremendously complex and expensive endeavor; power consumption and die areas are ultimately proxies for operating and manufacturing costs respectively. Furthermore, the crucial importance of integrated circuits has been highlighted in recent history by semiconductor shortages and geopolitical tensions, as well as corresponding economic policies that address these challenges.
This thesis investigates how these novel economic constraints fundamentally change how chip and computing system architectures are optimized compared to only evaluating against traditional performance metrics. First, this thesis investigates how semiconductor manufacturing and supply chains are vulnerable to disruptions. This work introduces a time-to-market model and Chip Agility Score to show how a chip’s architectural features affect its time-to-market and supply chain agility respectively.The model allows computer architects to quantify performance, cost, and supply chain-related trade-offs.
Second, this thesis investigates advanced computing sanctions that have placed performance restrictions and export controls on hardware designed for machine learning and large language models. This work demonstrates how these regulations ultimately influence chip architectures and shows how chip architectures can be further optimized while complying with regulations. Current regulations seem counterintuitive to how computer architects conventionally approach chip design. This thesis proposes an architecture-first approach for designing cost effective and practical regulations for target computing hardware while reducing the negative externalities of said policies.
By incorporating economic constraints into conventional performance evaluation, this thesis furthers our understanding of computer architecture and chip design in an uncertain world.
