Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT

Abstract

We present a novel parallel and pipelined fast Fourier transform (FFT) architecture for high-speed and low-power applications, a critical component in wireless communications and digital signal processors. The new FFT model implements a data-inverted Vedic multiplier in the FFT architecture, which reduces data switching activity in the input patterns to minimize dynamic power consumption and computational delay. The proposed architecture incorporates a low-power bit inversion (BI) multiplier scheme for a minimum number of complex multiplications with a high-speed partial product generation technique in FFT computation. This research focuses on the investigation and implementation of a modified butterfly unit as the best choice compared to other low-power and high-speed multipliers, such as Booth and Wallace multipliers for FFT processors. The BI multiplier design was synthesized in a field programmable gate array (FPGA), and the results show that the area efficiency could be improved by about 30 % and the power consumption and delay could be reduced by 56 %. The proposed FFT processor utilizes only 8 % of the available look-up tables (LUTs) with a 1:3 ratio in resource utilization and a 56 % reduction in delays compared to previous research. This makes this architecture best suited for high-speed wireless communications and 5G applications. This BI-Vedic multiplier is used in convolutions, FFT, and digital signal processing (DSP) filters where fast multiplication is critical. Throughput in applications with real-time signals is improved. It is also used in image and video processing and is critical for algorithms that manipulate pixels, scale, and compress data when many multiplications need to be performed quickly. IoT and embedded systems are beneficial for low-power systems as BI reduces power consumption and switching activity.