Dual-Bit FeFET for enhanced storage and endurance

Abstract

This work presents a novel Dual-Bit Ferroelectric Field-Effect Transistor (FeFET) structure that enables localized control of the ferroelectric (FE) layer through a segmented metal gate. This design allows for independent domain switching in distinct regions of the FE material, enabling the memory cell to store two discrete bits while maintaining robust read margins. Crucially, this approach eliminates the need for complex pulsing schemes, such as staircase write voltage pulses, which are typically required for multi-level cell (MLC) FeFETs. We demonstrate the functionality of this device through comprehensive TCAD simulations of read and write operations, considering both process variations and stochastic domain switching behavior. The device achieves a large memory window of 1.61 V even with reduced Program/Erase (P/E) voltages of ±3.3 V and a pulse duration of 1 μs–considerably improving efficiency and endurance. In contrast, conventional FeFETs require higher write voltages (i.e., ±4 V for 10 μs), which accelerate the underlying defect and trap generation, resulting in limited endurance. Our dual-bit design holds the potential for extending the endurance of FeFET-based crossbar arrays, which are crucial for AI accelerators. By effectively doubling the storage capacity, this approach reduces the frequency of weight reprogramming, addressing a key limitation in existing compute-in-memory architectures.

Introduction

The advent of memristive devices, capable of storing information in a non-volatile manner, has led to a wide range of applications exploiting this concept. One prominent application is in crossbar arrays, where memristive devices positioned at array intersections are used to implement bit-wise logic operations, with one operand stored directly within the device. This approach, known as compute-in-memory, leverages the non-volatile nature of memristive devices, allowing for both data storage and computation within the same architecture. Crossbar arrays have garnered significant attention for their structural simplicity and relevance to modern computing demands^{1, 2, 3–4}. The growing adoption of deep learning has intensified the need for fast and efficient matrix multiplication, and the grid-like configuration of crossbar arrays is inherently suited to such operations⁵. Implementations have demonstrated significant computational acceleration^{4,6, 7–8} and low power consumption⁹.

A key factor in crossbar array efficiency is the total size of the crossbar. When the parameters of a deep neural network (DNN) exceed the array’s storage capacity, a portion of the parameters must be cycled through the memristive devices, necessitating frequent reprogramming. This presents several challenges. In low-power applications, where frequent reprogramming and data loading incur substantial energy costs, the physical limitations of the crossbar array directly constrain its storage capacity. For example, the DNN’s size that can be implemented is capped by the number of weights the memristive devices can store. This often forces designers to adopt data partitioning strategies¹⁰, which add complexity to the overall system architecture. Furthermore, the continuous reprogramming required to cycle through DNN’s parameters poses significant challenges to device endurance. While endurance varies among memristive technologies, most suffer from limited endurance¹¹, especially when compared to conventional CMOS technology. This limitation severely restricts the maximum number of possible write operations that can be performed, impacting the long-term reliability and lifetime of the employed devices.

Since the discovery of ferroelectricity in hafnium oxide, Ferroelectric FET (FeFET) has rapidly emerged as one of the most promising non-volatile memory (NVM) technologies in recent years, offering full compatibility with CMOS processes^12,13. In these devices, the gate stack incorporates a zirconium-doped, thickened high-κ dielectric layer, where polarization states can be modulated through the application of an external electric field¹⁴. This field-driven programming mechanism significantly improves write efficiency compared to current-based programming schemes commonly employed in two-terminal devices^15,16.

A conventional FeFET stores one bit of information by leveraging the two stable polarization states of the FE layer, which correspond to binary logic levels¹⁷. The storage capacity of individual FeFET cells can be extended by utilizing intermediate, partially polarized states to store multiple bits per cell, a concept commonly referred to as multi-level cell (MLC) memory¹⁸. However, this MLC operation necessitates highly complex write schemes to carefully modulate the intermediate polarization levels¹⁹, as illustrated in Fig. 1A. Furthermore, the reliability of these intermediate states is significantly compromised by inherent variability, arising not only from process variations but also from the probabilistic nature of domain switching in the FE layer^15,18. This variability makes it increasingly difficult to distinguish between neighboring states in existing MLC-based FeFETs, as shown in Fig. 1B.

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Fig. 1

Structure and operation of a FeFET based MLC crossbar array.

A A conventional FeFET stack and the intermediate polarization levels that result from modulated programming pulses. Such devices require careful pulse generation, as the memory window margins between the different threshold voltage states are sensitive. B the narrow margins between the V_TH states make inferring the stored information accurately challenging in the presence of variability. C A crossbar array based on conventional FeFET transistors. For IMC purposes, the polarization of the FE layer and the gate input voltage are considered weight and input in a MAC operation, respectively.

In response to these challenges, we propose a novel dual-bit FeFET structure, which achieves enhanced storage density by splitting the metal gate along the source-drain axis. This structural modification introduces two independent gate terminals running parallel along the channel, thereby enabling localized control over separate regions of the FE layer. Each region can be, therefore, independently polarized, allowing the FeFET device to store two distinct bits of information in physically isolated regions within the same FE layer. This dual-bit structure maintains large read margins, ensuring high reliability in the presence of variability. Further, it eliminates the need for the sophisticated pulse-width modulation techniques typically required for MLC programming.

Beyond increasing storage density, our dual-bit FeFET design provides a robust solution for increasing the FeFET device endurance. In conventional FeFET, the gate electrode extends over the entire channel, inducing uniform stress on the FE layer during each program/erase cycle. This uniform stress accelerates fatigue within the FE material, which ultimately shortens the device’s operational lifetime. In contrast, the proposed split-gate structure confines the stress to only one localized region of the FE layer per operation, thereby distributing the stress and the induced degradation more effectively. Additionally, the reduced amplitude and duration of the write voltage in our dual-bit FeFET (±3.3 V for 1 μs compared to ±4 V for 10 μs) further mitigate the underlying defect generation, enhancing device endurance.

Results

By “virtually” combining two FeFET devices into a single structure, as depicted in Fig. 2, the storage capacity of a FeFET-based crossbar array is effectively doubled. Figure 2B illustrates the detailed structure of our proposed design, featuring two distinct gate contacts: the upper gate (U-Gate) and the lower gate (L-Gate), respectively.

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Fig. 2

When deployed in Edge Inferencing, conventional FeFET based arrays suffer from the need to frequently reprogram the cells with new weights, which quickly downgrades the device endurance.

A The proposed FeFET device can store two weights inside the same cell locally and independently, doubling the array’s capacity and improving endurance. B That is achieved by splitting the metal gate along the source-drain axis, enabling local polarization of the FE layer.

Split-gate device operation

The split-gate structure enables localized polarization of the FE layer directly beneath each respective gate contact. Figure 3A presents a cross-sectional view of the gate stack, oriented perpendicular to the source-drain axis. When programming voltages are applied to both gate contacts (for instance, positive voltages to induce downward polarization in both regions), the two regions of the FE layer under each gate are polarized independently. A downward polarization (P_FE+) results in a low-threshold voltage (LVT) state, characterized by high channel conductance, representing logic “1”. Conversely, an upward polarization (P_FE−) corresponds to a high-threshold voltage (HVT) state, with low conductance, representing logic “0”.

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Fig. 3

Structure and operation of the proposed split-gate FeFET.

A The split gates enable independent writing of dual bits into the device. A large positive pulse on one of the gates would positively polarize the FE area under it, which programs the corresponding bit with the logic value “1”. Similarly, A large negative pulse would result in logic “0”. B Reading schemes for accessing the lower and upper bits stored in the device in addition to the four possible combinations of stored bits and their corresponding polarization states. Unlike the conventional MLC, the two bits cannot be read in the same cycle since they require different biases. However, under this scheme, the FE cell can hold four combinations of two locally and independently stored bits.

During the write phase, the appropriate write voltage is applied to the targeted gate contact, selectively polarizing the underlying FE material and programming the desired bit. The localized polarization ensures that each bit is independently stored in its respective region of the FE layer. The read operation, as depicted in Fig. 3B, involves applying a specific read bias depending on the desired bit to access the stored information.

To represent the state of the entire split-gate device, we use the notation [Pol. L-Gate ∣ Pol. U-Gate], where the polarization of the lower and upper gates is explicitly noted. For example, storing logic “1” in both regions is denoted as [P_FE+∣P_FE+]. Figure 3B illustrates all four possible combinations of stored bits and their corresponding ideal read operations. For instance, when reading the lower bit, the U-Gate voltage is set to V_U-Gate = V_OFF and the L-Gate voltage is set to V_L-Gate = V_read. Consequently, the drain current is primarily determined by the polarization state of the L-Gate region. The current will be high if the lower gate stores logic “1” (i.e., [P_FE+∣X]) and low if it stores logic “0” (i.e., [P_FE−∣X]).

Read scheme validation

Figure 4A illustrates the device structure simulated in TCAD²⁰, where the voltage biases employed are V_read = 0 V and V_OFF = − 1.2 V. The baseline device is a 14 nm Fully-Depleted Silicon on Insulator (FDSOI) logic transistor, modified by incorporating a 10 nm thick FE layer to create a FeFET. The channel dimensions are 100 nm in both width and length, while each gate contact spans 45 nm, with a 10 nm gap separating the contacts. The I_D − V_G sweeps for reading the lower bit are shown in Fig. 4B, displaying the characteristics for all four possible polarization states. The device achieves leakage currents lower than 1e–10 A across all cases, while the on-state current exceeds 1e–5 A when storing a logic “1”. The read margin between the [P_FE+∣P_FE−] and [P_FE−∣P_FE+] states shows a separation of more than seven orders of magnitude in the measured current, indicating excellent read fidelity. As we simulate an ideal and symmetric device, the results for reading the upper bit, as seen in Fig. 4C, are mirrored accordingly. Figure 5 provides the electron density distribution in the channel during the read operation. Since electron density directly affects channel conductivity, it serves as a reliable indicator of the expected current. The electron density maps further confirm the localized operation of the split-gate architecture. The top left and bottom right maps depict the scenarios where the current is suppressed due to the “0” state being read, even when the other region stores a “1”. The applied V_OFF at the gate of the non-targeted bit suppresses the channel formation, ensuring low total drain currents. In contrast, the bottom left and top right maps correspond to high total drain currents, where a “1” bit is being read, and the elevated electron density under the gate forms a conductive channel.

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Fig. 4

To validate the split-gate dual-bit concept, TCAD simulations were used.

A Shows a 100 nm × 100 nm split-gate device asseen in TCAD with each gate contact covering 45% of the total channel width. It is important to keep the size of the middle part of the FE layer that has no overlaying gate as small as 10 nm width to avoid unwanted current flow. B Simulation results for reading the lower bit. C Simulation results for reading the upper bit. Read simulations showcase a mirrored behavior for the two reading cases, simplifying the overhead required to infer the stored values. In the idle case, the channel is suppressed with −1.2 V on bothsplit-gates. When reading one of the two bits, that suppression voltage islifted from the respective gate.

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Fig. 5

Further illustration of the reading scheme and the Independence of the two bits using electron density maps of the channel for the two cases [P_FE+∣P_FE−] and [P_FE−∣P_FE+].

Despite the positive polarization in the upper FE area of the [P_FE−∣P_FE+], we observe a low electron density in the channel when a −1.2 V is applied on the upper gate. These maps demonstrate the “and” operation that happens independently between the polarization of each FE section and the input on the respective gate. High electron density is only observed when the input on a given gate is logic “1”, and the FE area underneath that gate is polarized positively.

Write scheme validation

The write operation for the proposed dual-bit FeFET is validated using a device with dimensions identical to those discussed in the read validation. However, the FE layer is structured as a 20 × 20 array of smaller FE domains. Figure 6A illustrates the initial configuration of the FE layer, where domains are randomly polarized in either the P_FE+ (blue) or P_FE− (brown) state. This initialization is achieved by introducing a fixed charge concentration at the interface between the domains and the SiO₂ layer.

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Fig. 6

Our TCAD domain-based framework was used to validate the writing process.

A The switching development is presented throughout the writing phase, while two +3.3 V pulses are applied to each gate simultaneously. The FE layer is first initialized randomly with a 50% split of P_FE+ (Blue) and P_FE− (Brown) domains. B The programming pulse used on both gates consists of writing and relaxation phases. C Results of reading the lower bit after writing the device with all 2-bit combinations. Despite partial switching, the reading margin between the ON and OFF states is still large.

The programming pulse of 3.3 V (or the erase pulse of −3.3 V), as shown in Fig. 6B, is applied to the selected gate to program a logic “1” (or “0”) in the localized FE region beneath the gate. The vertical electric field generated by the applied pulse induces switching within the FE domains based on the input voltage. To ensure sufficient domain switching, the pulse duration is set to 1 μs, allowing adequate time for the majority of domains to flip. A single write cycle can program both gates simultaneously, as the switching of domains in one region has minimal impact on the other side of the FE layer. In Fig. 6A, the domain-switching pattern during the application of two programming pulses is depicted. By the end of the pulses, most negatively polarized domains have switched, transforming the upper and lower regions of the FE layer into low-threshold voltage states.

To confirm the stability of the polarization, the write pulse is followed by a relaxation phase with V_L-Gate = V_U-Gate = 0.0 V for 1 μs. The domain configuration remains unchanged after this relaxation period, demonstrating that the switching is neither transient nor spontaneous.

Although the 3.3 V pulse does not switch every domain to the desired state, a substantial on-state/off-state margin is still observed in Fig. 6C. The four curves correspond to reading the device after programming each of the four possible P_FE combinations. While increasing the pulse amplitude could improve domain switching uniformity, this would come at the cost of reduced endurance due to the accelerated fatigue of the FE material. Therefore, a balance is struck between sufficient on/off margin and long-term device reliability.

Analyzing the effects of variation

As previously outlined, our proposed dual-bit FeFET design transitions from partial polarization across the entire FE layer, which is a characteristic of MLC operation, to localized full polarization within targeted regions. This localized polarization approach significantly enhances resilience to random spatial variations, a common issue that affects conventional MLC operation, where partial polarization is highly susceptible to variability. By storing discrete binary states with full polarization, the design mitigates the effects of variation on device performance.

To validate this resilience, we tested the read operation on FeFET devices incorporating non-ideal post-program/erase configurations. FeFET devices are not only affected by variations in domain switching but are also subject to conventional sources of variation typical in traditional CMOS transistors. For the conventional variation sources of the underlying CMOS transistor, random dopant fluctuation, metal work-function variation, and line edge roughness were considered²¹. In addition, variations occurring due to the random location of polarized domains in a multi-domain FE layer are considered. By employing the baseline variation data for low V_TH and high V_TH states in FeFET devices from²¹, which accounts for conventional sources of variation, the total variance of the device can be obtained by combining it with the domain switching variance. This combination is valid under the assumption that the two variation sources are independent²¹. In this model, the different V_TH states are abstracted based on FE grid domain configurations, where variations in domain switching translate directly into changes in the V_TH state.

Our read scheme was rigorously tested on randomly generated FE grid configurations with a 5% switching variance from the two ideal states: [P_FE−∣P_FE+] and [P_FE+∣P_FE−]. These corner states were selected as they represent the most challenging cases due to their proximity, while the near-full polarization states are more easily distinguishable. Figure 7A shows the V_TH distributions of the L-Gate across 1000 randomly generated samples, incorporating both conventional sources of variation and a 5% domain switching variance. Despite this combined variation, the resulting distributions maintain a large memory window between the high V_TH and low V_TH states in the lower FE region. The lower-bit read operation preserves a robust average memory window of 1.61 V. Both V_TH states exhibit small standard deviations around 39.55 mV and 25.69 mV, well below the threshold required to disrupt reliable operation. Given the symmetry of the split-gate device, these results can be directly extended to the upper bit. For comparison, Fig. 7B illustrates the V_TH distributions for 1000 V_TH samples of a conventional FeFET MLC, combining all sources of variation. The results show a much smaller margin between the corner states.

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Fig. 7

The effect of variation on the memory window.

A L-Gate threshold voltage variation due to conventional sources combined with domain switching variance. Despite the variation, the device demonstrated a big margin between the two corner cases: [P_FE+∣P_FE−] and [P_FE−∣P_FE+]. Due to the symmetry of the device, U-Gate is expected to behave similarly thanks to the perfect symmetry of the operation and the structure. B The effect of conventional variation sources and domain switching variance on a conventional FeFET based MLC. Unlike our proposed structure, a conventional MLC shows a much smaller separation between logic levels.

In summary, the proposed split-gate FeFET structure demonstrates substantial resilience to variation. This robustness stems from the localized, spatially isolated storage of individual bits, rather than relying on intermediate V_TH or I_D levels, as in MLC designs. The binary distinction between the two states is based on the presence or absence of channel current, making small V_TH variances negligible. Consequently, this architecture allows for reduced write voltages, as full polarization is not required to maintain reliable data storage, as confirmed in the write validation section.

Discussion

In conventional FeFET designs, the gate contact spans the entire channel and FE layer, causing all domains to experience uniform switching when a voltage is applied. This uniform switching results in even fatigue across the FE material, progressively degrading the entire layer. In contrast, our proposed approach separates the upper and lower regions of the FE layer, allowing each to experience independent electric fields, thus creating heterogeneous fatigue patterns based on localized switching activity. This novel design opens the possibility of trading increased storage capacity for improved endurance by using only one region of the FE layer at a time, while keeping the other region idle. The device can continue to operate in this manner until the active region experiences fatigue, at which point the system can switch to utilizing the previously idle region. For this, we have conducted simulations analyzing the electric field across the device’s width (Fig. 8), as the electric field strength is the main driving factor behind endurance²². From this, we can see little bleed of the electric field into the inactive region, thus keeping it “fresh”. Moreover, the independent electric fields paired with adequate separation of the FE regions result in an operation free of read and write disturbance between the two stored bits.

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Fig. 8

Electric field across the FeFET device from the top down perspective.

The U-Gate region experiences a strong electric field from the applied voltage of 3.3 V. The L-Gate region’s applied voltage is set to 0 V, resulting in a weak field on the L-Gate side. This means no write disturbance as the electric field is too weak to flip domains on the L-Gate side. Additionally, it keeps the L-Gate side fresh and improves endurance.

Unlike a conventional FeFET MLC design, our device does not rely on accessing the intermediate states of the FeFET. Utilizing the intermediate states is more susceptible to variation and requires additional effort than our proposed write scheme. A pulse generator able to modulate both the amplitude and duration of the polarization pulses is necessary to access the intermediate states. Due to the random domain-switching process, an MLC write operation can result in overlapping states which leads to reading errors when accessing the content of the cells. This concern necessitates the use of variation mitigating techniques such as write-and-verify schemes to ensure a fault-free MLC operation. However, the costs of footprint, energy, and delay are increased as a result. On the contrary, our proposed design polarizes the individual FE sections in binary states; which alleviates the need for such schemes to achieve a reliable multi-bit operation.

Another significant advantage of this design is the potential to reduce the high polarization voltage used during write operations. Typically, a smaller Program/Erase pulse amplitude produces fewer switched domains, which means degraded switching uniformity. However, since our device exhibits strong separation between the two critical states, a less uniform switching does not compromise data integrity. Lowering the polarization voltage decreases the electric field applied to the FE layer, thereby slowing fatigue and extending the device’s operational lifetime²³. Further, the utilization of 3.3 V, particularly, aligns with the available IO voltage levels and pins of most integrated circuits, which simplifies power routing and eliminates the need for additional voltage levels and rails across the die.

The enhanced storage capacity enabled by our design allows for the scaling of larger DNN models within on-chip memory, reducing the need to stream parameters from external memory sources. By doubling the storage capacity, our approach facilitates the deployment of larger DNN models while mitigating external memory access bottlenecks. However, this improvement comes with a trade-off: the need for sequential reads of the two bits stored in a single device, which could impact read performance at the system level.

On the scalability of our proposed design: The two bits are separated by an uncontrolled area, with its size being a design parameter. The separation needs to balance the leakage current through the uncontrolled area (smaller separation is better) against the interaction of the electric fields between the adjacent regions (larger separation is better). Thus, scaling the width of the device may reduce the separation and requires reevaluating this trade-off. As the two gate metal strips run parallel to the source-drain axis, the length of the device can be scaled freely. The proposed structure requires an additional mask layer to realize the split metal gate, increasing the overall fabrication cost.

In summary, our split-gate design not only enhances storage density but also offers improved endurance and robustness by mitigating the effects of variability which classical MLC exhibits. The independent control of the upper and lower regions of the FE layer, coupled with the ability to reduce write voltage, provides a more dense and reliable solution for next-generation on-chip NVM and compute-in-memory AI accelerators.

Methods

Device calibration and FeFET modeling

The baseline structure for the device employed in this work is a 14 nm FDSOI logic transistor, as depicted in Fig. 9A. To ensure accurate replication of electrical characteristics, we have carefully calibrated the models within TCAD to match measurements reported in²⁴. The calibration of the I_D − V_G curves is conducted for both the saturation region (V_D = 0.9 V) and the linear region (V = 50 mV), with results presented in Fig. 9C.

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Fig. 9

FeFET device Calibration and modeling.

A Baseline 14 nm FDSOI logic transistor model. B To experiment with FeFET, the high-κ layer of the FDSOI is replaced with a 10 nm ferroelectric layer. C The baseline device is in TCAD used to calibrate and reproduce the I-V measurements. D Reproduced measurements of a 10 nm MFM Hf_0.5Zr_0.5O₂ capacitor using calibrated TCAD model. E Reproducing the P_FE effect using the Fixed Charges model.

The gate stack of the baseline device, as shown in Fig. 9A, is then modified to form the FeFET structure depicted in Fig. 9B. By replacing the high-κ dielectric with a 10 nm Hf_0.5Zr_0.5O₂ layer, we construct the FE gate stack necessary for the device under study. To ensure realistic FE behavior, we calibrate the internal Preisach model parameters within TCAD to reproduce the measured Q_FE-V_FE hysteresis loops reported for MFM capacitors²⁵ as seen in Fig. 9D.

To speedup the simulation process, we adopt a polarization emulation technique²⁶, wherein fixed charges are introduced at the oxide-FE interface. Using the calibrated Preisach model, we simulate the I_D − V_G characteristics at both the low-V_TH and high-V_TH states and adjust the injected fixed charge density to accurately match the model’s predicted behavior. Figure 9E presents the I_D − V_G loop comparison between the TCAD Preisach model and the fixed charge emulation technique. This emulation approach plays a critical role in our multi-domain-aware polarization framework²⁷, which is used across the experiments conducted in this work. A detailed summary of the TCAD parameters used in this study is provided in Table 1.

Table 1. Parameters used in TCAD

Description	Value
Technology node	14 nm FDSOI n-type
Used channel length/width	100 nm/100 nm
Channel doping	1e15 cm−3 Boron
Source/drain doping	1e20 cm−3 Phosphor
Ferroelectric thickness	10 nm Hf0.5Zr0.5O2
Domain size	5 nm × 5 nm
Saturation polarization	31 μC cm−2
Remnant polarization	25 μC cm−2
Positive fixed charges	18e12 C cm−2
Negative fixed charges	-12e12 C cm−2

Device structure

The TCAD Preisach model, along with our polarization emulation technique, is limited to representing a single polarization value per region. To accommodate the simultaneous existence of different polarization states within the FE layer, the layer is divided into multiple regions. Specifically, we divide it into three parallel strips along the source-drain axis: two outer regions, each covered by their respective split-gate metal contact (L-Gate and U-Gate), and a neutral section located between them. The two outer regions store one bit of information each and are programmed independently via their corresponding gate contacts. The outer regions have a width of 45 nm each, covering the full channel length, while the neutral middle section spans 10 nm of the total width. At these widths of the channel and middle section, a reliable operation can be ensured regardless of the polarization state of the middle section. An entirely positively switched 10 nm middle section does not result in unwanted on-states. This structure is primarily employed to verify the read scheme, as detailed in the results section.

For write validation and the analysis of variation effects on device functionality, a domain-based structure is utilized. This structure, previously introduced in the multi-domain framework of ref. ²⁷, is designed to study FE switching dynamics at the domain level. In this setup, the FE layer consists of a grid of smaller blocks, referred to as domains, which are assigned Q_fix concentration values to represent their respective polarization states. The dimensions of the gates (L-Gate and U-Gate) remain consistent with the prior structure, while a smaller domain size of 5 nm is employed, resulting in a 20 × 20 grid, as listed in Table 1. This domain-based grid structure enables partial switching of the FE layer, manifesting in various V_TH levels²⁸. For the FeFET to achieve a low V_TH state, the majority of domains within the FE layer must be in the P_FE+ polarization state.

Acknowledgements

We would like to thank Om Prakash for his support in the TCAD device calibration.This work was supported by the German Research Foundation (DFG) under grant AM 534/5-1 (NN-Thunder, project: 506419033).

Author contributions

H.A. conceived and supervised the idea. K.N guided the device modeling and simulations. M. B and S.T performed the TCAD experiments and analyzed the data. All authors contributed to the manuscript writing and provided feedback.

Funding

Open Access funding enabled and organized by Projekt DEAL.

Data Availability

The data that support the plots within this paper and other findings of this study are available from the corresponding authors on reasonable request.

Code availability

The codes that support the findings of this study are available from the corresponding authors upon request.

Competing interests

The authors declare no competing interests.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

References

1. Soliman, T et al. First demonstration of in-memory computing crossbar using multi-level cell FeFET. Nat. Commun.; 2023; 14, 2023NatCo.14.6348S1:CAS:528:DC%2BB3sXitFalsrjK [DOI: https://dx.doi.org/10.1038/s41467-023-42110-y] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/37816751][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10564859]6348.

2. Park, S; Lee, D; Kang, J; Choi, H; Park, J-H. Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In₂Se₃ for stacked in-memory computing array. Nat. Commun.; 2023; 14, 2023NatCo.14.6778P1:CAS:528:DC%2BB3sXit1CgtbfI [DOI: https://dx.doi.org/10.1038/s41467-023-41991-3] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/37880220][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10600126]6778.

3. Soliman, T. et al. Ultra-low power flexible precision FeFET based analog in-memory computing. In Proc. 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 29.2.1–29.2.4 (IEEE, 2020).

4. Kim, M-K; Kim, I-J; Lee, J-S. Cmos-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks. Sci. Adv.; 2022; 8, eabm8537.2018RSCAd..8.8537K1:CAS:528:DC%2BB38Xht1GhtbrP [DOI: https://dx.doi.org/10.1126/sciadv.abm8537] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/35394830][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8993117]

5. Ielmini, D; Wong, H-SP. In-memory computing with resistive switching devices. Nat. Electron.; 2018; 1, pp. 333-343. [DOI: https://dx.doi.org/10.1038/s41928-018-0092-2]

6. Soliman, T. et al. Efficient FeFET crossbar accelerator for binary neural networks. In Proc.2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP), Manchester, UK, pp. 109–112 (IEEE. 2020).

7. Hu, M. et al. Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication. In Proc. 53rd Annual Design Automation Conference, DAC ’16, Association for Computing Machinery, New York, NY, USA, Article 19, 1–6 (2016).

8. Yin, X et al. Deep random forest with ferroelectric analog content addressable memory. Sci. Adv.; 2024; 10, eadk8471.1:CAS:528:DC%2BB2cXht12nsrfI [DOI: https://dx.doi.org/10.1126/sciadv.adk8471] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38838137][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC11152117]

9. Youngblood, N. Coherent photonic crossbar arrays for large-scale matrix-matrix multiplication. IEEE J. Sel. Top. Quantum Electron.; 2023; 29, pp. 1-11. [DOI: https://dx.doi.org/10.1109/JSTQE.2022.3171167]

10. Kim, Y., Kim, H., Ahn, D. & Kim, J.-J. Input-splitting of large neural networks for power-efficient accelerator with resistive crossbar memory array. In Proc. International Symposium on Low Power Electronics and Design, ISLPED ’18, Article No. 41, pp. 1–6, (Association for Computing Machinery, New York, NY, USA, 2018).

11. Lanza, M et al. Memristive technologies for data storage, computation, encryption, and radio-frequency communication. Science; 2022; 376, eabj9979.1:CAS:528:DC%2BB38XhsFGnt7jJ [DOI: https://dx.doi.org/10.1126/science.abj9979] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/35653464]

12. Beyer, S. et al. FeFET: A versatile CMOS compatible device with game-changing potential. In Proc.2020 IEEE International Memory Workshop (IMW), Dresden, Germany, pp. 1–4 (2020).

13. Salahuddin, S; Ni, K; Datta, S. The era of hyper-scaling in electronics. Nat. Electron.; 2018; 1, pp. 442-450. [DOI: https://dx.doi.org/10.1038/s41928-018-0117-x]

14. Karbasian, G. et al. Ferroelectricity in HfO2 thin films as a function of Zr doping. In Proc. 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, pp. 1–2 (2017).

15. Khan, AI; Keshavarzi, A; Datta, S. The future of ferroelectric field-effect transistor technology. Nat. Electron.; 2020; 3, pp. 588-597. [DOI: https://dx.doi.org/10.1038/s41928-020-00492-7]

16. Slesazeck, S., Schroeder, U. & Mikolajick, T. Embedding hafnium oxide based FeFETs in the memory landscape. In Proc.2018 International Conference on IC Design & Technology (ICICDT), Otranto, Italy, pp. 121–124 (2018).

17. Salahuddin, S. et al. FeFETs for Near-Memory and In-Memory Compute. In Proc.2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 19.4.1–19.4.4 (2021).

18. Müller, F. et al. Multilevel operation of ferroelectric fet memory arrays considering current percolation paths impacting switching behavior. IEEE Electron Device Lett. 44, 757–760 (2023).

19. Wu, J. et al. Adaptive circuit approaches to low-power multi-level/cell FeFET memory. In Proc.2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, pp. 407–413, (2020).

20. Synopsys, Inc. Sentaurus TCAD (Version S-2021.06) [Computer software]. https://www.synopsys.com (2021).

21. Chatterjee, S; Thomann, S; Ni, K; Chauhan, YS; Amrouch, H. Comprehensive variability analysis in dual-port FeFET for reliable multi-level-cell storage. IEEE Trans. Electron Devices; 2022; 69, pp. 5316-5323.2022ITED..69.5316C1:CAS:528:DC%2BB38XisFOrsLrK [DOI: https://dx.doi.org/10.1109/TED.2022.3192808]

22. Francois, T et al. Impact of area scaling on the ferroelectric properties of back-end of line compatible Hf0.5Zr0.5O2 and Si:HfO2-based MFM capacitors. Appl. Phys. Lett.; 2021; 118, 062904.2021ApPhL.118f2904F1:CAS:528:DC%2BB3MXktlWqur8%3D [DOI: https://dx.doi.org/10.1063/5.0035650]

23. Sharma, A. A. et al. High speed memory operation in channel-last, back-gated ferroelectric transistors. In Proc.2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 18.5.1–18.5.4 (2020).

24. Liu, Q. et al. High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond. In Proc.2013 IEEE International Electron Devices Meeting, Washington, DC, USA, pp. 9.2.1–9.2.4 (2013).

25. Jerry, M. et al. Ferroelectric FET analog synapse for acceleration of deep neural network training. In Proc.2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 6.2.1–6.2.4 (2017).

26. Ni, K. et al. On the channel percolation in ferroelectric FET towards proper analog states engineering. In Proc. 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 15.3.1–15.3.4 (IEEE, 2021).

27. Thomann, S., Ni, K. & Amrouch, H. Joint modeling of multi-domain ferroelectric and distributed channel towards unveiling the asymmetric abrupt DC current jump in ferroelectric FET. In Proc. ESSDERC 2022-IEEE 52nd European Solid-State Device Research Conference (ESSDERC), Milan, Italy, pp. 336–339 (2022).

28. Jerry, M. et al. A ferroelectric field effect transistor based synaptic weight cell. J. Phys. D: Appl. Phys.51, 434001 (2018).