Algorithm profiling for architectures with dataflow accelerators

Abstract

Dataflow computing has proved to be more efficient for certain high-performance computing algorithms. The prerequisites are that there is enough parallel calculation to cover the overhead of executing instructions on the dataflow hardware until the first result is ready. This is often true with algorithms that work with big data and that can process multiple iterations independently, e.g., while simulating certain phenomena in many elementary volumes. However, dataflow hardware runs typically at an order of magnitude lower frequencies compared to the control-flow processor. From a programmer’s point of view, programming dataflow architectures is considerably harder than programming control-flow architectures. As a result, it is not always obvious whether programming dataflow architectures for certain algorithms is worth the effort needed. Therefore, there is a need for a programmer to be able to predict the outcome of programming for dataflow architectures in terms of accelerating program execution and power savings. This article presents a newly developed tool that a programmer can use for profiling control-flow algorithms and estimating the acceleration possibilities using the dataflow hardware.