Content area
This thesis focuses on the process and device simulation of semiconductor quantum dot arrays manufactured in production 22nm FDSOI CMOS technology in order to investigate the optimal process waivers and device structure changes needed to implement tuneable tunnel-coupled quantum dots towards the realization of entangled qubit gates. The simulations were conducted using the commercial Sentaurus TCAD software package. The simulator was first calibrated based on room-temperature I-V and transconductance measurements of minimum size transistors %and coupled quantum dot arrays to ensure that the channel material parameters, such as mechanical strain, and structural transistor parameters match measurements. Next, the simulator was used to predict the impact of top gate pitch, back gate and top barrier gate architecture on the tunnel-coupled quantum dot characteristics. Some of the resulting coupled quantum dot arrays with coupling controlled by the backgate were laid out by other students in the group with necessary process waivers and structural changes, manufactured by a commercial foundry, and verified through measurements at room temperature and 2-4 Kelvin by the author and other students in the group, where tunnel coupling controlled by the backgate was observed. Simulations of arrays with different barrier gate implementations indicate that a barrier gate in the M1 layer or a top gate with varied width or overlap height can also control the potential barrier between dots. These simulations demonstrate how the process flow may be altered to accommodate multi-qubit gates, or in the case of the gate in the M1 layer, how a multi-qubit gate could be realized within the constraints of the commercial 22nm FDSOI process.