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Field-Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Architectures (CGRAs) represent two prominent categories of reconfigurable architectures, each offering unique advantages and trade-offs. Traditionally, research on CGRA architectures and their associated Computer-Aided Design (CAD) tools has been empirical, involving the modelling of CGRA fabrics and mapping applications onto them. An open-source framework, Coarse-Grained Reconfigurable Architecture Modeling and Exploration (CGRA-ME), has emerged to facilitate CGRA architecture and CAD research. CGRA-ME provides researchers with an API to model CGRA architectures using C++. It also enables automated application mapping onto modelled CGRAs and the generation of Verilog code for the CGRA architecture from the architectural model.
This thesis introduces several extensions to CGRA-ME, focusing on frontend compilation, architecture modelling, and mapping strategies. Firstly, we propose a frontend compiler capable of generating hyperblocks for arbitrary kernels, leveraging recent Multi Level Intermediate Representation (MLIR) support. Secondly, our architecture modelling extensions incorporate the ability to model elastic architectures in single and multiple contexts and the capability to model predicated architectures for both elastic and static CGRA architectures.
Thirdly, we present a novel mapping algorithm utilizing simulated annealing and PathFinder techniques for application mapping on both elastic and static CGRA architectures. Then we introduce enhancements to the simulated annealing cost function and a novel clustering algorithm to speed up the mapping process. Additionally, we propose a dynamic scheduling algorithm that adjusts the depth of a schedule to underlying architectures, by coupling both scheduling and routing.
Lastly, we present a contribution targeted for high-level synthesis (HLS). HLS tools take in high-abstraction code such as C and synthesize it into a hardware circuit in a Hardware Description Language (HDL). In our research, we extend the LegUp HLS framework to support the synthesis of transactional memory to HDL for FPGAs.
