Content area
The Electronic Design Automation (EDA) industry relies on rigorous testing metrics, utilizing extensive randomized simulation environments to functionally test a device and employing formal verification (FV) in the most critical areas. However, FV using traditional approaches poses a significant challenge, especially when dealing with complex designs.
The advent of High-Level Synthesis (HLS), which has led to the development of circuit description languages such as SystemC, has enabled the representation of devices more abstractly. Several tools, including STATE, SPIN, and VerCors, have been created to fulfill this purpose.
This thesis aims to investigate whether formal verification at the SystemC level can verify larger designs faster than at the lowest level, namely in the SystemVerilog (SV) language. To this end, one tool was chosen for each verification level.
The work concludes that the high-level verification is still in its early stages of investigation, with the performance of the tool being slower in comparison to the low-level tool. All designs verified operated based on clock cycles, thus the expected advantages of high-level abstraction were not fully realized. Furthermore, the high-level tool lacks the optimization present in the low-level tool, contributing to its reduced efficiency.