Power Delivery and Voltage Regulation for Neuromorphic Computing Architectures Including in Memory Compute RRAMs

Abstract

This dissertation presents and evaluates novel power delivery and voltage regulation techniques for neuromorphic computing architectures. It also evaluates data conversion for Hybrid Memories and then proposes a power efficient SAR ADC architecture for a Resistive Random-Access Memory (RRAM) based in-memory computing module. The proposed circuit schemes are designed in 40nm and 65 nm CMOS to address the critical challenges of voltage stability, transient response, and power efficiency in Switch Capacitor and Hybrid Buck Converters. First, a multitude of regulation design techniques target different performance parameters of a 2:1 Switch Capacitor Voltage Regulator (SCVR). Some highlights of these designs include an analog ripple reduction scheme that achieves up to twice the reduction in output voltage ripple when compared to the baseline scheme, enabling more reliable programming of multi-level resistive states in RRAM cells. Second, the divided reference slice scheme achieves the least droop and quickest recovery across a 10X load step, critical for maintaining consistent voltage levels during programming events in RRAM crossbar arrays. Third, the switch width modulation scheme that controls the switch on/off ratio is proposed to help in power reduction proportional to the load current, addressing the dynamic power requirements of neuromorphic computing workloads. The dissertation further introduces a new architecture of Flying Capacitor Multilevel Converter (FCML) specifically optimized to cater to low Supply demands for In-Memory Computing RRAMs, which effectively reduces the effective resistance at the switching node and removes the flying capacitor voltage imbalance. This architecture enables reliable ultra-low voltage operation essential for energy-efficient neuromorphic computing and establishing a pathway for practical deployment of edge AI applications with unprecedented energy efficiency. The work concludes by presenting a VCM- based Low Power SAR ADC design optimized for In-Memory Computing RRAM Array