Design of a Robust IEEE Compliant Floating-Point Divide and Square Root Using Iterative Approximation

Abstract

In this work, an IEEE 754 compliant normalized floating-point divide and square root unit is presented that utilizes iterative approximation. This research provides a robust architecture that allows multiple formats and all IEEE 754 rounding modes while still exhibiting high-performance. Moreover, this thesis presents a design that adheres to the IEEE 754 2019 standard as well as demonstrating methods for rounding results to all five rounding modes using iterative approximation. Performance, Power, and Area estimates are determined from physical synthesis using ARM-based standard cells in a TSMC 28nm process. This thesis also presents comparisons with other implementations and demonstrates the efficiency of the approach presented here.