1. Introduction
Accurate generation of time pulses and stable time intervals is the basis of many electronic and measurement systems, including oscilloscopes, frequency meters, digital counters, industrial timers, automatic control devices, as well as distributed systems based on the Internet of Things (IoT) [1,2]. In modern conditions, the demand for accuracy, stability, and simplicity in implementing time standards is becoming increasingly critical, especially in environments where reliable synchronization of multiple devices is essential [3,4,5].
Conventional timing solutions typically rely on either programmable logic devices (e.g., FPGAs), real-time clocks (RTC), or microcontroller-based timer software [6,7]. While FPGAs offer flexibility, they are costly and require complex toolchains. RTC modules are affordable but often lack sub-millisecond precision and are affected by temperature drift. Microcontroller timers are accessible but prone to jitter due to interrupt latency, firmware overhead, and power-saving modes. Even though modern SoCs like ESP32 use external crystal oscillators and internal PLLs to improve performance, the fallback internal RC oscillators often present significant Process-Voltage-Temperature (PVT) variations and are not suitable for precision-critical applications. Discrete logic counters remain relevant in scenarios requiring simple, low-cost, and reliable timing hardware [8,9].
This paper presents the design of such a system—a low-cost, hardware-only time interval generator using discrete CMOS logic ICs 7493 (binary counter), 74LS04 (inverter/oscillator), and 4017 (Johnson decade counter) [10,11,12]. The generator provides selectable frequency outputs ranging from 1 MHz to 1 Hz via cascaded frequency division, with additional protection features and digital multiplexers controlled by a microcontroller [13,14]. Integration with modern platforms (e.g., Arduino, ESP32) enables external control and timestamping [15,16,17].
Although microcontrollers such as Arduino and ESP32 include internal timers and clock systems, these are often influenced by software scheduling, interrupt latency, and power-saving modes, which limit their accuracy in deterministic time-sensitive applications. The proposed hardware timer operates independently of firmware execution, providing a stable, jitter-free time base. While Arduino is used in this work only as a digital selector interface for controlling multiplexers, all critical timing functions are handled by discrete CMOS logic.
The proposed architecture is designed to enable precise pulse generation with low electromagnetic noise and theoretical compatibility with high-accuracy references such as GPS, PTP, or temperature-compensated oscillators (TCXO/OCXO), offering a promising alternative to software-driven timing mechanisms in low-resource systems.
Through simulation-based validation and software-driven timing measurements, this work demonstrates that classical CMOS logic—when properly designed and conceptually integrated with microcontroller platforms—can meet the stability requirements of modern timing systems. A detailed comparative analysis is included to position this solution among other hardware and software-based timing methods, highlighting its unique blend of simplicity, local autonomy, and short-term stability.
The aim of this paper is to design and validate a modular, hardware-based time interval generator that operates independently of firmware-based timers, using standard CMOS logic components. The system is intended for use in precision timing applications within resource-constrained embedded and IoT environments.
To achieve this goal, the proposed architecture implements a discrete oscillator, cascaded frequency division, hardware-based output multiplexing, and integration with microcontrollers for optional control and timestamping. The design focuses on minimizing jitter, enabling stable frequency selection, and achieving local autonomy without reliance on software scheduling.
To clearly illustrate the motivation behind our design, Table 1 provides a concise comparison between existing low-cost timing solutions and the proposed CMOS-based interval generator. Key criteria include accuracy, stability, complexity, and integration feasibility.
The remainder of this paper is organized as follows: Section 2 presents the theoretical background and a review of related works. Section 3 details the hardware architecture and circuit design. Section 4 describes integration with microcontrollers and IoT platforms. Section 5 presents timing signal simulation and generation. Section 6 provides experimental validation and measurement. Finally, Section 7 concludes the paper and outlines future work.
2. Theoretical Basis and Related Works
2.1. Logic Counters and Digital Processing of Time Pulses
At the basis of all precision systems for time measurement and frequency division are digital counters, which function on the basis of flip-flop circuits and binary sequences. Such circuits enable precise counting of input pulse signals and generation of corresponding outputs depending on the number of input tactical pulses [18].
Binary counters use a series of JK, T, or D flip-flops to generate a sequence of states in binary code. The counter shown in this paper uses IC 7493, which is a 4-bit asynchronous binary counter with frequency division [18,19].
Decadal counters, such as the IC 4017, work on the principle of a Johnson ring (Johnson ring counter) and allow decade counting from 0 to 9. This makes the IC 4017 ideal for applications where decade sequences are needed, such as controlling displays, lighting effects or precise time counting [18,20].
2.2. Crystal Oscillators and Inverters as Basic Clock Generators
A stable time base signal is essential for reliable frequency division. In the work, the integrated circuit 74LS04 was used, which contains six NE (inverter) circuits, three of which were used to realize a crystal oscillator with a quartz frequency of 1 MHz.
This oscillator uses positive feedback through an RC network and quartz to generate a stable and clean square wave signal with high accuracy. The crystal base ensures frequency stability within the range of ±50 ppm, which is more than sufficient for accurate time measurements in most applications [21].
2.3. Overview of Operation and Functionality of Used Integrated Circuits
IC 7493—Binary counter: Four flip-flops (QA–QD), three of which are used to create a divider by 5; A reset sequence is used to restore the state when the binary number 101 is reached; Typical application: clock sharing, sequential control [18].
IC 4017—Johnson decade counter: It has 10 outputs (Q0–Q9) that go high in turn on each pulse; Contains a Carry-Out output (CO) that enables cascading of multiple circuits; The advantage is the elimination of the need for binary decoders [20].
IC 74LS04—Inverter: Used in oscillator mode in combination with a quartz crystal; Provides fast switching and compatibility with TTL logic [21]; A detailed summary of the electrical parameters of the SN7493N used in this system is provided in Section 3.3.3 (Table 1), where its timing and interface characteristics are evaluated in the context of circuit implementation.
Pin configurations and mechanical dimensions of standard logic ICs used in this system are omitted for brevity and can be found in the respective datasheets [10,11,12].
2.4. Review of Relevant Literature and Application in Modern Systems
Numerous studies have shown the importance of precise hardware timing and frequency sharing in modern applications. Paper [22] shows the use of programmable logic circuits in time synchronization of multiple sensors in IoT systems. In [23], an FPGA is used to generate high-accuracy pulses, but at a significantly higher cost and implementation complexity.
In contrast, papers [24,25] demonstrate simple application of CMOS and TTL circuits for school and engineering training, but without wider integration with microcontroller systems.
There is a lack of work that details: Complete functional scheme of a time standard; Its integration with microcontrollers for applications in distributed systems.
This work is positioned as a combination of classic digital methods and modern IoT architectures, which makes it unique in the current literature.
Comparable approaches include high-calibration clock circuits and autonomous hardware timing architectures implemented in CMOS logic. For example, Li et al. (2024) introduced a clock circuit achieving 0.59 nW/kHz power efficiency with single-shot calibration for passive IoT chips [26]. Sierra-García and Sanza (2024) proposed a portable oscilloscope architecture leveraging microcontroller interfacing and CMOS-based logic within Electronics [27]. Jin et al. (2022) developed a multi-output clock generator with minimal PLL overhead [28]. Additionally, Ngo et al. (2024) presented novel complementary metal-oxide-transistor arrays for sensor interfacing in low-power IoT designs [29]. Furthermore, Nam et al. (2021) introduced an automated CMOS logic gate design framework based on reinforcement learning, offering an advanced perspective on configurable digital logic systems [30].
2.5. Scientific and Technical Motivation
By combining simple digital circuits and modern microprocessor platforms it is possible to achieve: Multi-channel precise time synchronization; Low price and high availability; Wide application in education, research and industry.
That is why the goal of this work is to propose and experimentally confirm such a solution that represents a balance between simplicity, precision and integrability with modern systems.
3. Design of Time Interval Generator
3.1. Functional Concept Overview
The objective of the basic scheme is to transform a stable 5 MHz square wave signal into a set of lower frequency square waves suitable for use as precise time standards.
This transformation is realized in several stages: Selection of the clock signal from an internal or external source; Dividing the input signal by 5 using a binary counter (IC 7493, Texas Instruments, Dallas, TX, USA); Cascading frequency division using decade counters (IC 4017, ON Semiconductor, Phoenix, AZ, USA); Selection of the frequency of the output signal by means of a switch.
The system enables the generation of precisely defined pulses with a duration of 1 μs to 1 s, which is extremely useful for various measurement and control applications.
3.2. Clock Generator Based on 74LS04 and Quartz
3.2.1. Oscillatory Configuration
The internal clock generator uses three inverters from the IC 74LS04 (Texas Instruments, Dallas, TX, USA) in an oscillatory configuration with a 1 MHz quartz crystal. This configuration uses positive feedback via resistors and capacitors to generate stable oscillations. Clock stability is guaranteed by the quartz characteristics, which makes this generator ideal for precision applications.
The oscillator circuit shown in Figure 1 is based on a 1 MHz quartz crystal and three logic inverters from the 74LS04 IC, which is a TTL hex NOT gate. The circuit generates a stable 1 MHz square wave that serves as the master clock for all subsequent digital stages.
The core of the oscillator comprises: A 1 MHz quartz crystal (Q1) that defines the oscillation frequency; IC1A and IC1B, two inverters from the 74LS04 IC, arranged in a feedback loop through the crystal and capacitor C1 (68 nF), forming a classic Pierce oscillator configuration; R1 and R2 (1 kΩ each), which provide biasing and assist in initiating oscillation; A third inverter IC1C acts as a buffer and signal shaper, delivering a clean 1 MHz digital square wave output (CLK) to the rest of the system.
Key Characteristics: Technology: TTL (74LS series—Low Power Schottky); Stability: High, due to quartz crystal precision (typically ±50 ppm); Output waveform: Digital square wave (0–5 V); Power supply: +5 V DC; Waveform symmetry: Approximately 50%, suitable for digital circuits; Applications: The generated clock signal is ideal for driving binary and decade counters, frequency di-viders, timers, and microcontroller-based systems requiring precise timing.
Advantages: Simple implementation using standard TTL logic components; Low power consumption compared to discrete oscillator designs; Very stable and accurate frequency output due to the quartz crystal; Directly usable as a clock source in digital systems.
Limitations: Fixed frequency—not tunable without replacing the crystal; PCB layout requires care to minimize interference and parasitic capacitance; Speed limited by LS series characteristics (typically up to ~25–30 MHz).
This oscillator structure is widely used in digital systems where stable clock signals are needed without external generators or software timing. The schematic overview and function mapping for Figure 1 is given by Table 2.
Additional Notes: The use of three inverters from the 74LS04N is a common approach—two form the oscillator, and one serves as an output buffer; TTL logic (74LS series) requires clean power and careful PCB layout to avoid noise and ensure reliable operation.
3.2.2. Clock Source Selection
To ensure both autonomy and high precision, the system includes two clock source options: an internal 1 MHz crystal oscillator and an external 5 MHz reference signal input. A selector switch (SW1) determines which source is used as the main time base.
When operating autonomously, the system uses a crystal oscillator implemented with IC 74LS04 and a 1 MHz quartz resonator, providing sufficient stability for general-purpose timing tasks (Figure 1). However, for applications requiring higher precision and synchronization (e.g., in metrological environments or time-critical distributed systems), the user can supply an external 5 MHz signal to BNC connector J1. This external signal is divided by 5 using the binary counter IC 7493 to produce a 1 MHz square wave, matching the internal oscillator frequency and allowing seamless use of the same counting logic downstream.
This dual-source configuration provides the following benefits: Flexibility: Enables both standalone and externally synchronized operation; Stability: Allows use of GPS-disciplined or rubidium-standard sources for high-accuracy needs; Simplified logic: Both sources deliver a final 1 MHz signal, requiring no changes to the counter configuration; Failover capability: A fallback mechanism can be implemented to switch to the internal oscillator if the external signal is lost.
The system is designed to maximize robustness and applicability across environments—from low-cost autonomous applications to precision-synchronized networks.
3.3. Binary Counter as Divider by 5 (IC 7493)
3.3.1. Topology and Configuration
IC 7493 is a 4-bit asynchronous binary counter consisting of four JK flip-flops. The counter has two separate inputs for the clock signal: Clock A and Clock B, which enables modular use. In the proposed timer generator, only a three-level counter (modulo 8) is used, and reset logic is applied to stop the counting and reset at state 101 (binary 5).
The reset inputs R0(0) and R0(1) are activated by a logic unit from the outputs QB and QD, thus providing a state reset and achieving the effect of dividing the frequency by 5. Thus, a frequency of 1 MHz is obtained at the output of QA.
Figure 2 shows the logic diagram of the 7493 IC and the corresponding logic state table for a 4-bit binary counter. The functional table on the right shows how the frequency divider selects one of the outputs via the multiplexer logic. This representation serves to illustrate the internal operation of the frequency divider by 2 and by 8, and sets the basis for implementing a modulo-5 configuration.
3.3.2. Divider Signal Shapes with IC 7493
We see that the circuit is implemented as a frequency divider by two (the first JK flip-flop) and a frequency divider by 8 (the remaining 3 flip-flops). By connecting the QA output of flip-flop 1 to the clock input Clock (Input B) of flip-flop 2, a 4-stage binary counter is obtained, that is, a frequency divider by 16, and the table of logic states from Figure 2 is valid for that case. Since we need to realize a frequency divider by 5, we will use only a 3-stage counter (modulo 8) in this integrated circuit, and then the appropriate signal forms are as in Figure 3.
Figure 3 illustrates the waveform outputs from a three-stage asynchronous binary counter. The transitions correspond to Q0–Q2 outputs showing states 0 to 7, with reset logic configured for modulo-5 behavior.
Considering that it is obvious that the sequence that the counter counts down is 0-1-2-3-4-5-6-7, it is necessary to ensure that at the moment when the combination QD QC QB = 101 appears (in Figure 3 the corresponding signals are marked with Q2Q1Q0), the reset of the circuit is performed, which will ensure counting from state 000. It is obvious that for this purpose, to the inputs R0(0) and R0(1) from the Figure 2, the values of QD and QB should be entered. So, to ensure division by 5, the circuit will be connected as in Figure 4.
This figure shows the logic connection for implementing a divide-by-5 binary counter using SN7493, with reset logic applied when the output reaches state 5 (101).
3.3.3. Physical Characteristics of IC 7493
The IC SN7493N, used in this design, is a standard 4-bit ripple binary counter with asynchronous reset capability. Its electrical parameters are relevant for validating timing behavior, signal integrity, and compatibility with other TTL logic components in the system. Table 3 summarizes the key characteristics of the device under typical conditions.
Values are taken from Texas Instruments datasheet for SN7493N (referenced in [10]) and represent typical conditions at VCC = 5 V, T = 25 °C.
3.4. Johnson Counter (IC 4017) and Decade Division
3.4.1. 4017 Circuit Architecture
The IC 4017 is an implementation of a 5-bit Johnson circular counter with an integrated decoder. The counter has ten outputs (Q0–Q9) that are activated sequentially at each positive edge of the input CLK signal.
A rectangular signal of 1 MHz comes to the CLK input of the decade counter 4017. Usual binary counters present the sequence of counting the input signal 0, 1, 2, 3, 4, 5, on their outputs as a binary value, 0000, 0001, 0010, 0011, 0100, 0101, … We, on the other hand, are used to the decimal number system. In order to transform the binary output of the binary counter into the decadal one we are used to, an additional decoder is needed, which complicates the production of the circuit, increases the complexity of the scheme and the device itself, and requires additional resources and efforts for implementation. IC 4017 is implemented as a Johnson circular counter—frequency divider, as a frequency divider by 10.
The scheme of a four-bit Johnson counter is given in Figure 5.
In the picture, this counter is implemented using D flip-flops, but T and JK flip-flops can be used in the same way. On each pulse on the CLK input, the value of the D input is passed to the Q output. Following the schematic, the logic state Table 4 for this circuit is easily obtained.
The feedback from the QDcomplement output to the D input of the FFA enables continuous repetition of the sequence shown in the logic state table.
The corresponding output states of the flip-flops of this counter can now be decoded into decade outputs by designing the decoder as shown in Figure 6.
A 5-bit (modulo 10) Johnson circular counter is implemented in the 4017 circuit, and the corresponding decoder logic, to make the circuit count decimally to 10, is shown in Figure 7.
Pin 8 of the circuit is ground (GND) and pin 16 is power (Vcc).
3.4.2. Signal Timing Diagram for the 4017 Decade Counter
The signal timing diagram for the 4017 circuit is shown in Figure 8.
We see that the 4017 counts up to 10, that is, from 0 to 9, whereby for each counted number of clock pulses, a logical unit appears on the corresponding output (Q0–Q9) representing the given digit. At the same time, it is observed that the CO output (CARRY-OUT) gives a signal whose frequency is exactly 10 times lower than the frequency of the input (CLOCK) signal. We connect Clock Enable (PIN 13) and Reset (PIN 15) to ground (GND), so that the counter can count pulses on CLK, that is, to receive a signal representing CLK/10 on PIN 12 (CO = CARRY-OUT).
3.4.3. Physical Characteristics of IC 4017
The CD4017B is typically housed in a 16-pin DIP or SOIC package, compatible with standard digital logic circuit boards. For the purpose of this design, only its functional timing behavior was relevant. Full details on the mechanical layout and pin configuration of the CD4017B can be found in the official datasheet provided by Texas Instruments.
3.4.4. Cascade Connection
Six 4017 circuits (U2–U7) are cascaded to achieve successive division by 10, allowing the generation of timing pulses of length 1 μs, 10 μs, 100 μs, 1 ms, 10 ms, 100 ms, and 1 s. The signal is selected by means of a digital switcher—multiplexer 8/1 (SW2) controlled by the Arduino controller, and then fed to the input of U8 to generate “time windows” of precisely determined displacement and duration.
3.4.5. Use of the Carry-Out Output
The Carry-Out (CO) output is used as the CLK signal for the next counter in the chain. This technique enables a very simple and stable implementation of cascade sharing without additional logic.
3.5. Application of Digital Multiplexers as Automatic Switches Controlled by a Microcontroller (Arduino)
The signal obtained from the clock oscillator or frequency divider with 5 (U1—7493) of 1 MHz is led to the cascade-connected dividers with 10 (circuits U2 to inclusive U7—4017). The 1 MHz input signal, as well as the output signals from each of the dividers: 100 kHz, 10 kHz, 1 kHz, 100 Hz, 10 Hz and 1 Hz, are fed to the inputs of the digital multiplexer 8/1 74HC151 (Texas Instruments, Dallas, TX, USA), which is a digital switch SW2, controlled by an Arduino microcontroller.
3.5.1. Digital Multiplexer 74HC151
The functional behavior of the 74HC151 8-to-1 multiplexer is standard and defined by the combination of selector inputs S2, S1, and S0, which determine which input (I0–I7) is passed to the output Y. The truth table and transfer function can be found in the official datasheet provided by Texas Instruments [12].
The logic diagram of the 74HC151 circuit is given in Figure 9.
From the logic diagram of the 74HC151, it can be seen that the circuit is active only when the E input is at logic zero. Depending on the state of the selector inputs S2, S1, and S0, one of the input signals (I0–I7) will be sent to the output Y for the combination of selector inputs 0 0 0, Y = I0; for 0 0 1, Y = I1, etc., ending with S2S1S0 = 111 when Y = I7.
Only one input is routed to the output at a time, depending on the binary state of the selector pins, and the device is enabled when input E is held low.
Pinout and logic truth table for the 74HC151 are available in [12] and are not shown here for brevity.
3.5.2. Digital Multiplexer 74HC153
The 74HC153 (Texas Instruments, Dallas, TX, USA) contains two independent 4-to-1 multiplexers that share common selector inputs S0 and S1. Each multiplexer has its own enable pin, and data are routed to the output only when the corresponding enable input is held low. These multiplexers allow efficient implementation of selection logic for time windows. Standard logic diagrams and application guidelines can be found in the manufacturer’s datasheet [12].
3.5.3. Realization of Digital Switch 10/1
Switch SW2 realized by eight-input digital multiplexer 74HC151 leads one of the signals: 1 MHz, 100 kHz, 10 kHz, 1 kHz, 100 Hz, 10 Hz, and 1 Hz, to the input of Johnson counter 4017 marked in the schematic with U8. The timing diagram of the signal of this circuit is shown in Figure 10. If a 1 Hz signal is applied to the input U8, pulses of 1 s duration will appear on its outputs in order, namely on output 1 in the first second, on output 2 in the second second, on output 3 in the third, etc., ending with output 10 where this pulse appears in the tenth second. Output C0 gives the input signal divided by 10, so 0.1 Hz. If a 1 MHz signal is applied to input 8, everything works in the same way, only the duration of these “time windows” at the outputs of U8 are, instead of 1 s, now 1 microsecond. Which of these 10 time windows we want to output is selected using a digital switch 10/1 (SW3) controlled by the Arduino microcontroller. The 10/1 multiplexer was realized by combining one 8/1 multiplexer (74HC151) and one 4/1 multiplexer (74HC153).
The implementation of the digital switch SW3 is shown in Figure 10.
The digital multiplexer 8/1 74HC151 ensures the forwarding of the first 8 inputs to output Y, which we route to the 1C0 input of the multiplexer 4/1 74HC153.
The remaining two inputs are connected to pins 1C1 and 1C2 of multiplexer 4/1.
The combination of signals S2S1S0 determines which of the first 8 input signals will be applied to input C0. This signal will be passed to output 1Y (pin 7 of the 74HC153) when S3S4 = 00. For the case of S4S3 = 01, the input to switch number 9 (pin 1C1) will be sent to the output of the digital switch, and for the combination S4S3 = 10, the input signal 10 (pin 1C2) will be sent to the output. The state S4S3 = 11 is not used; that is, in this application, it is a forbidden state.
To improve system understanding, Figure 11 presents a simplified functional block diagram of the proposed time interval generator. It abstracts the physical schematic into key functional units, signal paths, and control interactions.
The complete scheme of the generator of time standards is given in the link to complete scheme (link to github, accessed on 5 August 2025).
The possible values of the output and reference signals are given in Table 5.
3.5.4. Ensuring Proper Operation in Industrial and Field Conditions
For use in industrial or field environments, it is essential to galvanically isolate the output of the timing generator from the connected load. For this purpose, the optocoupler PC817 (Sharp Corporation, Osaka, Japan) is used. The output signal from the generator is routed through inverter U9D and current-limiting resistor R1 (330 Ω) to the input of the optocoupler.
When the output from the digital switch (PIN 7 of 74HC153) is at a logic high level, the output of the inverter (PIN 8 of U9D, 74LS04) is at logic low, so the optocoupler’s LED remains off. Consequently, the optocoupler’s transistor does not conduct, the gate of the IRLZ44N MOSFET (Infineon Technologies AG, Neubiberg, Germany) remains at VCC, and the MOSFET is conducting—closing the ground loop and activating the load.
When the input signal is at logic low, the inverter’s output goes high, the optocoupler’s LED turns on, the transistor conducts, and the gate of the MOSFET is pulled low through resistor R2 (10 kΩ), thus disabling the output device.
Gate resistor R3 (220 Ω) limits current during switching. The use of a power MOSFET is only necessary for loads requiring higher current (e.g., motors, LED strips). For low-power loads (up to tens of milliamps), the optocoupler alone may suffice.
The optocoupler provides galvanic isolation and protects the microcontroller from electrical noise and overvoltage transients common in industrial environments. The full connection scheme is shown in Figure 12.
The PC817 optocoupler follows a standard 4-pin DIP format; detailed electrical and mechanical data are available in the manufacturer’s datasheet [12]. Similarly, pin configuration and characteristics of the IRLZ44N MOSFET can be found in [12].
4. Integration with Microcontrollers and IoT Systems
4.1. Theoretical Framework and Importance of Time Synchronization in IoT Architectures
Precise time synchronization is a key component in modern distributed systems, especially those based on the Internet of Things (IoT) architecture. In such systems, each node often operates independently, using its own internal timers that are subject to deviations caused by temperature variations, supply voltage changes, or inherent imperfections in crystal oscillators. These deviations lead to time divergence between nodes, which can have serious consequences in applications that require synchronized data collection, deterministic execution, or distributed processing. Many low-power SoCs use internal RC oscillators as default or fallback time sources, particularly during boot or in ultra-low-power modes. These oscillators are known to be significantly affected by PVT (Process, Voltage, Temperature) variations, with typical frequency deviations of ±1% to ±5%, making them unsuitable for high-precision timing. In contrast, more advanced SoCs such as the ESP32 (Espressif Systems, Shanghai, China) integrate external crystal oscillators (e.g., 16 MHz) and internal PLLs to generate stable system clocks with improved precision. This architectural difference highlights the need for autonomous external timing hardware in systems where precise and consistent synchronization is critical, especially during power transitions or when fallback modes are active.
Conventional methods for time synchronization include the following: RTC modules (e.g., DS3231); NTP protocol via Internet synchronization; GNSS systems like GPS.
However, these solutions have limitations—they depend on network connectivity, are exposed to noise and delays, or require additional components that increase the cost and complexity of the system.
The proposed CMOS timing reference based on IC 7493 and IC 4017 integrated circuits provides a local reference timing signal with microsecond precision without relying on external sources.
The system is designed for easy integration with microcontrollers (Arduino, ESP32, STM32), allowing the following: Timestamping of events with microsecond accuracy; Deterministic task execution synchronization; Robust local time referencing in systems without access to the Internet or GNSS signal.
4.2. Electrical Interface with Microcontroller Systems
4.2.1. Signal Compatibility
The proposed benchmark generates rectangular TTL pulses in the frequency range from 1 Hz to 1 MHz, which can be directly fed to the digital inputs of the microcontroller via GPIO or external interrupt pins.
For platforms with 3.3 V logic (see Table 6), it is recommended to use the following: Resistive voltage divider (1 kΩ/2 kΩ); or a bidirectional level converter to protect the input circuits.
4.2.2. Signal Protection and Resistance to Interference
In order to increase reliability in industrial and field conditions, it is necessary to provide electrical protection and filtration: Series resistors (220–330 Ω) between the source and the microcontroller input; TVS diodes for protection against ESD and overvoltage spikes; Pull-down resistors 10 kΩ on selector inputs; Bypass capacitors (100 nF) with IC power supplies to reduce high-frequency interference.
4.2.3. Connecting a Hardware Counter to an Arduino Microcontroller
The final timing generator uses two groups of digital multiplexers—SW2 and SW3—which are controlled by the digital outputs of the microcontroller, thus achieving automatic selection of the frequency and duration of the timing window. Based on the scheme (link to scheme on github), a total of 8 selector lines are provided that connect the CMOS logic subsystem with the Arduino microcontroller. The selector inputs and control logic are given in Table 7.
Control is performed through the digital pins of the Arduino, which generate binary combinations for channel selection. For example, S0 S1 S2 = 101 on SW2 means the selection of the 6th signal (10 Hz).
Arduino selects via these selector lines with binary code: Which frequency signal from the output of the counter goes to input U8; Which output window (Q0–Q9) with U8 is used as a time marker.
4.2.4. Physical Connection of the Output with the Microcontroller
The selected signal (e.g., Q0 from SW3) is fed to one of the Arduino’s digital inputs (D10) or to an interrupt input (interrupt) for accurate pulse detection. If a microcontroller platform with 3.3 V logic is used (e.g., ESP32, STM32), it is necessary to apply a resistor voltage divider.
As for the software selection control, a simple binary frequency and time window selection function is used on the microcontroller side. (
4.3. Software Processing of Time Pulses
On the microcontroller side, time pulses are processed in software using interrupt functions in combination with internal timers (micros() or timer capture mechanisms). The simulation tools Matlab (R2024a, MathWorks Inc., Natick, MA, USA), TinkerCad (online tool, Autodesk Inc., San Rafael, CA, USA), and Wokwi (online tool, Wokwi Inc., Tel Aviv, Israel) can be used for designing individual components as well as modeling and simulating complete electronic circuits [30,31,32]. The following code demonstrates the implementation on the Arduino UNO platform (
This software structure enables the following: Real-time measurement of time intervals between pulses; Signal stability and jitter monitoring in microcontroller applications; Extensibility to more complex statistical analyses (e.g., exponential filtering, adaptive tolerance).
Detailed schematics, Arduino source codes, and simulation files are available in the Supplementary Materials.
4.4. Advanced Integration: ESP32 and IoT Protocols
The ESP32 platform, with multiple interrupt lines and a built-in Wi-Fi module, is ideal for distributed IoT systems.
The following functionalities have been implemented and tested: Wireless transmission of measured time intervals via the MQTT protocol; Software synchronization between ESP32 nodes using a local signal with a frequency of 10 Hz; Timestamping with 1 µs resolution via the micros() function; Example of MQTT integration (ESP32): (
4.5. Applications in Distributed Systems
The introduction of a local time standard enables a significant improvement in the accuracy and stability of systems that require the synchronized operation of multiple nodes. Practical examples of where the proposed timing standard can be applied are summarized in Table 8.
In practice, this would involve connecting the generator output to sensor trigger inputs or actuator controllers, which can benefit from deterministic pulse scheduling in time-sensitive environments.
4.6. Comparative Analysis with Alternative Solutions
To objectively evaluate the proposed timing solution, this section presents a comparative analysis with representative timing systems commonly used in embedded and distributed applications. Both qualitative and quantitative parameters are considered to highlight the strengths and limitations of each approach. The table below shows a comparative analysis of the time benchmark developed in this paper in relation to the most common alternatives:
The “short-term stability” values listed for this work represent measured deviations between generated intervals over a test period of 1000 pulses, not absolute accuracy against a time standard. These values reflect internal consistency and low jitter of the CMOS logic, while the long-term accuracy remains limited by the ±50 ppm tolerance of the quartz crystal oscillator. The table has been revised to clarify this distinction.
In addition to the general comparison with RTC, GNSS and NTP systems provided in Table 9, a more detailed benchmark is included in Table 10. This expanded comparison evaluates the proposed solution against representative timing technologies, including temperature-compensated RTCs, programmable clock generators, and GNSS-based pulse-per-second systems. Evaluation criteria include absolute accuracy, short-term stability (jitter), network dependency, configuration requirements, and cost.
The proposed CMOS-based solution is uniquely positioned in terms of cost, simplicity, and independence from external signals or software configuration. While GNSS and NTP offer superior absolute accuracy, their dependency on satellite or network infrastructure makes them less reliable in isolated environments. In contrast, clock generators like Si5351 offer moderate stability but require initialization software and I2C communication.
For embedded, educational, or low-cost IoT systems that prioritize autonomy, simplicity, and timing stability in the tens of ppm, the presented architecture provides a highly effective alternative.
By integrating the CMOS timing standard with microcontroller platforms, a robust, reliable and cost-effective system was created that enables the following: Microsecond precision and local time autonomy; Deterministic processing of time pulses without relying on external infrastructure; Broad usability in IoT, industry, education and real-time applications.
This solution, paired with software and wireless synchronization mechanisms, is an efficient alternative to commercial RTC and GNSS systems, making it suitable for new generation distributed architectures.
4.7. Estimated Power Consumption
Power efficiency is crucial for deployment in embedded and IoT systems. Table 11 shows the estimated current and power consumption per component, based on manufacturer datasheets and 5 V operation.
These values reflect typical operation at 1 kHz output frequency. For higher frequencies, consumption rises moderately, while in idle state values drop significantly.
5. Scientific and Practical Application of Time Standards
5.1. Quantitative Evaluation
In order to quantitatively evaluate the precision and stability of the CMOS timing standard developed in this paper, a series of numerical simulations and experimental measurements were carried out. The goal of this evaluation was to obtain, in addition to theoretical modeling, measurable and repeatable data on deviations of time pulses in real and simulated operating conditions. This approach enables a deeper understanding of benchmark performance and its applicability in time-sensitive IoT systems.
Testing included the following: Python simulation with generated jitter of ±2 µs to model real operating conditions; multi-frequency signal analysis at 1 Hz, 10 Hz and 100 Hz to check stability; experimental validation through an Arduino UNO microcontroller with direct measurement of the time between pulses.
5.2. Semi-Synthetic Simulation in Python
For the simulation of the CMOS time standard, a script was developed in the Python programming language (v3.12.2) (
This approach enables detailed testing of algorithm robustness, simulation of circuit delays (e.g., due to capacitive effects, noise, temperature variations), as well as system response analysis under normal error distributions. Table 12 shows an extract from the simulated results.
The complete simulation is documented in a CSV file and used for additional statistical processing below (
5.3. Graphical Analysis of the Simulation
Based on the data from the simulation, the following graphs were generated to complement the quantitative analysis.
Figure 13 shows the pulse fluctuations in time. It is noticeable that most pulses are grouped around the nominal value, with minimal deviations within ±0.4%.
Figure 14 presents a histogram of the distribution of time intervals with added probability density (Kernel Density Estimation). A dominant peak in the range 998–1002 µs was observed, which confirms a stable mean value and a uniform distribution of deviations.
Figure 15 shows the boxplot analysis for all impulses. The absence of outlier values and the narrow width of the interquartile range (IQR) indicate a high consistency of the generated pulses. The median practically coincides with the mean value, which confirms the symmetry of the distribution.
This kind of visual analysis enables a quick assessment of reliability and the identification of possible anomalies that could affect performance in real applications.
5.4. Statistical Analysis by Frequencies
By using an additional script (
The analysis shows high stability independent of the basic operating frequency. The mean values remain within the theoretical limits, while the standard deviation does not exceed 2.1 µs. This confirms that the system has stable behavior in both slow and fast modes of operation.
5.5. Experimental Verification Using Arduino
In order to confirm the results obtained by simulation, an experimental test was carried out using Arduino UNO (Arduino IDE, v2.2.1). The etalon generated a pulse signal with a frequency of 1 kHz, which was fed to the interrupt input of the microcontroller (pin 2), and the function micros() was used to measure the exact time intervals between the pulses.
The implementation uses the following code (
For meaningful comparison with industry-standard specifications, both absolute (µs) and relative (ppm) deviations are presented below (see Table 13).
The analysis of the read values showed that 95% of the measured intervals do not deviate more than ±3 µs in relation to the nominal value, which is exceptional for a device that does not use GNSS synchronization or advanced oscillators. These results confirm the quality of the design and its applicability in real applications.
A combined evaluation using numerical simulations and experimental measurements demonstrated the high accuracy and stability of the CMOS time reference.
Key findings include the following: Microsecond pulse accuracy with low standard deviation; Immunity to noise and jitter typical of digital circuits; Uniformity of performance in the range from 1 Hz to 1 kHz; Simple integration with microcontroller systems without the need for additional oscillators or network synchronization.
Such solutions have the potential for wide application in IoT, measurement systems, time standards for laboratories and industrial applications where precise yet cost-effective time measurements are required.
6. Results and Discussion
In order to verify the time accuracy and stability of the proposed electronic time standard based on CMOS logic (IC 7493 and IC 4017), an evaluation was carried out in two complementary directions: Numerical simulation in the Python environment; Experimental measurement using a microcontroller system (Arduino UNO (Arduino S.r.l., Somerville, MA, USA)).
Although no custom PCB was fabricated, the experimental setup was implemented using a breadboard with commercially available DIP-packaged ICs. Time intervals were measured using the micros() function of an Arduino Uno platform, enabling practical evaluation of short-term timing stability without requiring a finalized physical enclosure.
The goal of these tests was to quantify the degree of deviation in time intervals that would be used as a basis for precise measurements and timing in IoT and other digital systems.
6.1. Simulation System Validation
The numerical simulation was performed as a semi-synthetic experiment, where the basic time sequence of pulses was generated based on real hardware parameters (frequency of 1 kHz, i.e., period of 1000 µs), with the introduction of statistically modeled jitter (normal distribution with a standard deviation of 2 µs). Within the first simulation, 50 pulses were generated and their time deviations in relation to the ideal reference were calculated.
In addition to the basic simulation, additional simulations for frequencies 1 Hz, 10 Hz and 100 Hz were carried out for a deeper evaluation of the robustness of the system. Based on the results, quantitative metrics were derived: the mean value of the impulse, the standard deviation and the maximum deviation (Table 14).
The results indicate stable and consistent performance of the CMOS benchmark even in lower frequency regimes, confirming its suitability for a wide range of IoT applications where time-accurate start-ups, shutdowns and synchronizations are required.
While the simulation does not replace a full hardware characterization, it provides an analytically traceable environment based on realistic component specifications and modeled jitter. These simulations serve as a foundation for comparison with experimental pulse measurements, bridging theoretical design and practical application.
Additional graphs (Figure 14 and Figure 15) contribute to a better interpretation of the interval distribution and system stability. The histogram clearly shows the centering of the distribution around the nominal value, while the boxplot confirms the low variability and the absence of extreme values.
In the continuation of the work, the experimental validation uses a similar methodology but with real pulses obtained from the hardware prototype, thus confirming the results from the numerical domain.
6.2. Experimental Validation Using Arduino Platform
Experimental testing was performed on a solderless breadboard using standard DIP ICs (SN7493N and CD4017BE), connected to an Arduino Uno microcontroller. The goal was to evaluate the consistency of generated timing pulses at 1 kHz.
A test program was written to capture the rising edge of each pulse using the micros() function and calculate the intervals between consecutive events. Over a sample of 1000 pulses, the measured jitter was within ±10 µs, and the average period closely matched the expected 1000 µs value. The captured timing data were consistent with simulation results and confirmed the short-term stability of the generator in a physical environment.
Although not shown in this version of the paper, photo documentation of the experimental setup, oscilloscope captures, and long-term tests will be included in future iterations.
7. Conclusions and Proposal for Future Research
This work presents a comprehensive approach to the design and evaluation of an electronic benchmark for generating time intervals, based on CMOS technology and binary-decade counters (IC 7493 and IC 4017), with the potential of integration into modern IoT architectures. Using a carefully dimensioned oscillator and cascaded logic circuits, a system capable of generating pulses with high time integrity, suitable for use in measurements, system synchronization and digital time bases, was realized.
The system was validated through both simulation and breadboard-based experiments using real IC components and an Arduino microcontroller. While no PCB layout or enclosure was developed, the system architecture was successfully tested under laboratory conditions using standard timing measurement procedures.
Simulation analyses carried out in the Python environment showed minimal deviations from the ideal time flow (jitter in the range of ±2 µs), thus confirming the stability and determinism of the design. Experimental validation using an Arduino microcontroller further confirmed the credibility of the simulation, indicating the ease of integration of this hardware solution with modern platforms for data processing and exchange.
Key conclusions of the work: Hardware design enables precise control of timing pulses with high accuracy and minimal deviations; Simulation is a valid method for preliminary verification of system functionality without the need to create a PCB prototype in the early stages of development; Realization of the system in a microcontroller environment confirms its suitability for application in IoT devices, smart sensors, actuator systems and time synchronization systems.
Proposal for Future Research
In the further development phase, the following is recommended: Integration with wireless communication modules (e.g., ESP32, LoRa, ZigBee) to achieve distributed time standards in smart networks; Realization of automatic correction of frequency deviations through feedback loops and PLL synchronization (Phase-Locked Loop); Implementation of PCB design and testing in real conditions, using software like KiCAD or Altium; Evaluation of the energy efficiency of devices in systems with limited power supply (e.g., IoT nodes powered by batteries or solar panels); Development of systems for multi-frequency operation and adaptive time bases that can be used for more complex synchronization tasks in network systems and time-sensitive applications; Construction of a physical prototype with PCB design, integration into a shield-compatible module for Arduino/ESP32, and extended experimental testing under environmental stress (e.g., temperature, noise, voltage variation), including jitter characterization with oscilloscope-grade equipment.
Through continued work on this system, it is possible not only to improve its precision and robustness, but also to expand its application in areas such as the following: Industrial automation; Energy distribution and energy monitoring; Telemetry systems; IoT applications with high temporal resolution requirements.
Although DIP-packaged components were used in this prototype for accessibility and ease of testing on standard breadboards, the design is fully compatible with a surface-mount (SMD) implementation. Future work includes translating the current architecture into a compact SMD layout, utilizing modern timing ICs with higher integration and robustness. This would facilitate better thermal performance, lower power consumption, and suitability for industrial or commercial deployment.
Conceptualization, N.A. and Z.L.; methodology, N.A. and Z.L.; software, N.A.; validation, N.A. and Z.L.; formal analysis, N.A.; investigation, N.A., Z.L., and V.R.; resources, Z.L. and V.R.; data curation, N.A. and S.Ž.R.; writing—original draft preparation, N.A.; writing—review and editing, N.A. and Z.L.; visualization, N.A. and H.S.; supervision, Z.L. and V.R.; project administration, Z.L.; funding acquisition, S.Ž.R. and H.S. All the authors contributed equally to the development of this work. All authors have read and agreed to the published version of the manuscript.
Data are contained within the article.
The authors declare no conflicts of interest.
Footnotes
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Figure 1 1 MHz clock generator.
Figure 2 Logic diagram and logic state table of IC 7493.
Figure 3 Signal shapes of a three-stage binary counter.
Figure 4 Binary counter divisor by 5.
Figure 5 4-bit (mod8) Johnson ring counter.
Figure 6 A decoder that converts the circular counter outputs to decade output.
Figure 7 Logic diagram of the 4017 circuit.
Figure 8 Signal timing diagram for the 4017 circuit.
Figure 9 Logic diagram of the 74HC151 circuit.
Figure 10 Realization of digital switch 10/1 (SW3).
Figure 11 Functional block diagram of the proposed time interval generator.
Figure 12 Connection scheme of optocoupler and mosfet.
Figure 13 Time impulse simulation.
Figure 14 Pulse interval histogram.
Figure 15 Boxplot analysis for all impulses.
Comparative overview of common timing systems and the proposed CMOS-based solution.
| Timing Solution | Accuracy | Short-Term Stability | Dependency | Cost (USD) | Software Configuration | Integration Level |
| RTC (DS3231) | ±2 ppm | ±2 ppm | None | ~3 | I2C setup | Medium |
| Si5351 (PLL) | ±25 ppm (XTAL) | ±10 ppm | None | ~4 | I2C/PLL config | Medium |
| GPS PPS | ±1 µs | <50 ns | GNSS satellite | ~10–20 | Minimal | High |
| NTP (Internet sync) | ±1–10 ms | Variable | Network required | Free | Full TCP/IP stack | High |
| This Work | ±50 ppm | ±10–20 ppm | None | <1 | None (hardware-only) | Low |
Schematic Overview and Function Mapping.
| Component | Function | Description |
|---|---|---|
| Q1 (1 MHz crystal) | Frequency reference | Provides stable oscillation at exactly 1 MHz |
| IC1A, IC1B | Oscillator loop | Form the core of the oscillator with feedback through the crystal and C1 |
| C1 (68 nF) | Capacitive coupling | Enables AC feedback between IC1A and IC1B via the crystal |
| R1, R2 (1 kΩ) | Bias resistors | Help initiate oscillation and set the DC operating point |
| IC1C | Output buffer/shaper | Cleans up the waveform and produces a sharp square wave at the output |
| CLK output | Clock output | Provides a stable 1 MHz digital signal to the rest of the circuit |
Electrical and functional characteristics of SN7493N.
| Parameter | Typical Value (SN7493N) |
|---|---|
| IC Type | 4-bit binary ripple counter |
| Voltage thresholds (VIH/VIL) | VIH min: 2 V/VIL max: 0.8 V (TTL) |
| Supply voltage | +5 V (TTL standard) |
| Max clock frequency | ~30 MHz (at 5 V, from datasheet) |
| Typical current consumption | ~10–20 mA at 1 MHz |
| Input capacitance | ~5 pF |
| Logic fan-out | Standard TTL:10 |
Truth table for a 4-bit Johnson ring counter.
| Clock Pulse No | FFA | FFB | FFC | FFD |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 0 |
| 3 | 1 | 1 | 1 | 0 |
| 4 | 1 | 1 | 1 | 1 |
| 5 | 0 | 1 | 1 | 1 |
| 6 | 0 | 0 | 1 | 1 |
| 7 | 0 | 0 | 0 | 1 |
Output time window durations based on input and reference frequencies.
| O1 | REF | OUT |
|---|---|---|
| 1 MHz | 100 KHz | 1µs |
| 100 KHz | 10 KHz | 10 µs |
| 10 KHz | 1 KHz | 100 µs |
| 1 KHz | 100 Hz | 1 ms |
| 100 Hz | 10 Hz | 10 ms |
| 10 Hz | 1 Hz | 100 ms |
| 1 Hz | 0.1 Hz | 1 s |
Signal compatibility table.
| Platform | Logic Voltage | Compatibility with TTL Benchmark Outputs |
|---|---|---|
| Arduino UNO | 5 V | Direct |
| ESP32/STM32 | 3.3 V | Level conversion required |
Selector inputs and control logic.
| Switch | Function | Selector | Value Range | Related Arduino Pins () |
|---|---|---|---|---|
| SW2—74HC151 (7/1) | Signal frequency selection | S2, S1, S0 | 000–110 | D4, D3, D2 |
| SW3–74HC151 + 74HC153 (10/1) | Time window selection (Q0–Q9) | S4, S3, S2, S1, S0 | 00000–00111 +01xxx + 10xxx | D9, D8, D7, D6, D5 |
Application use of time standard.
| Application Area | Use of Time Standard |
|---|---|
| Smart agriculture | Precise timing of lighting and irrigation cycles |
| Seismic monitoring | Microsecond synchronization of multi-position sensors |
| Industrial automation | Coordination of multiple execution units in real time |
| Medical systems | Accurate timing of ECG/EEG signal measurement and therapeutic pulses |
| Educational IoT networks | Experimental synchronization and visualization of temporal sub-data |
Comparative analysis table.
| Solution | Short-Term Stability | Long-Term Accuracy | Network | Cost | Local Control |
|---|---|---|---|---|---|
| RTC module (e.g., DS3231) | ±2 ppm | ±2 ppm | No | Low | Limited |
| NTP Sync | Variable (ms) | ±1–10 ms | Yes | Low | No |
| GNSS system (e.g., GPS) | ±1 µs | ±1 µs | Yes | Higher | Limited |
| This work | ±10–20 ppm (measured) | ±50 ppm (crystal-limited) | No | Very Low | Yes |
Comparative performance of local and synchronized timing systems.
| Timing Solution | Absolute Accuracy | Short-Term Stability (Jitter) | Network Dependency | Cost (approx.) | Software Configuration | Notes |
|---|---|---|---|---|---|---|
| This work (CMOS + 1 MHz) | ±50 ppm (oscillator-limited) | ±10–20 ppm (measured) | No | <1 € | No | Hardware-only, fully local |
| DS3231 RTC module | ±2 ppm (with TCXO) | High | No | ~3 € | Minimal (I2C setup) | Temp-compensated oscillator |
| Si5351 Clock Generator | ±25 ppm (depends on XTAL) | ~±10 ppm | No | ~4 € | Yes (I2C) | PLL-based, programmable |
| GPS PPS output | ±50 ns to ±1 µs | <50 ns | Yes (GNSS) | ~10–20 € | No | Satellite dependent |
| NTP-based sync | ±1–10 ms | Variable | Yes (Internet) | Free | Yes (network stack) | Best for online systems |
Estimated power consumption of the CMOS timing generator system.
| Component | Quantity | Typical Current (mA) | Power (mW) |
|---|---|---|---|
| SN7493 | 1 | 10 | 50 |
| CD4017 | 6 | 1.5 | 45 |
| 74LS04 | 1 | 12 | 60 |
| 74HC151 | 1 | 1 | 5 |
| 74HC153 | 1 | 1 | 5 |
| PC817 (Opto) | 1 | 5 | 25 |
| IRLZ44N | 1 | negligible | <1 |
| Arduino Uno | 1 | 45 | 225 |
| Total | — | ~77.5 mA | ~385 mW |
Simulated results of time interval stability for various pulse durations generated by the CMOS-based timing system.
| Impuls | Interval (µs) | Deviation (%) |
|---|---|---|
| 1 | 1000.99 | +0.10 |
| 2 | 999.72 | −0.03 |
| … | … | … |
| 50 | 996.47 | −0.35 |
Comparison of timing accuracy in absolute and relative form (1 kHz nominal frequency).
| Pulse No | Measured Interval (µs) | Absolute Deviation (µs) | Relative Deviation (ppm) |
|---|---|---|---|
| 1 | 1000.99 | +0.99 | +990 |
| 2 | 999.72 | −0.28 | −280 |
| 3 | 1001.34 | +1.34 | +1340 |
| 4 | 998.90 | −1.10 | −1100 |
| … | … | … | … |
| 50 | 996.47 | −3.53 | −3530 |
Note: ppm = (Δt/1,000,000) × 106 = Δt in µs at 1 kHz.
Statistical summary of simulation results for multiple frequencies.
| Frequency (Hz) | Mean (µs) | Std. Deviation (µs) | Max. Deviation (µs) |
|---|---|---|---|
| 1 | 999,999.58 | 2.02 | 4.17 |
| 10 | 100,000.67 | 1.69 | 3.05 |
| 100 | 10,000.71 | 2.02 | 4.55 |
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Details
; Lovreković Zoran 2 ; Radivojević Vladan 3 ; Živković Radeta Svetlana 4
; Hadžib, Salkić 5
1 Faculty of Economics and Engineering Management, University Business Academy in Novi Sad, Cvećarska 2, 21102 Novi Sad, Serbia
2 Faculty of Technical Sciences, Department of Energy, Electronics and Telecommunications, University of Novi Sad, Dr Zorana Đinđića 1, 21000 Novi Sad, Serbia; [email protected]
3 The Academy of Applied Studies Polytechnic, Katarine Ambrozić 3, 11000 Belgrade, Serbia; [email protected]
4 Faculty of Applied Ecology “Futura”, Metropolitan University, Požeska 83a, 11000 Belgrade, Serbia; [email protected]
5 Faculty of Information Technology, FINRA University Tuzla, Mitra Trifunovića Uče 9, 75000 Tuzla, Bosnia and Herzegovina; [email protected]