Content area

Abstract

With the stagnation of Moore’s Law and the breakdown of Dennard Scaling, hardware designers are increasingly turning to heterogeneous architectures to achieve higher performance and energy efficiency. Heterogeneous design composes complete systems from specialized, modular components optimized for specific applications or markets. This modular approach contrasts with traditional homogeneous architectures, which use identical processors to handle diverse workloads. By leveraging the unique strengths of each component, heterogeneous systems not only outperform their homogeneous counterparts but also enable faster time-to-market across a broad range of use cases. Such specialization has been key to advances in low-power embedded systems and data-intensive machine learning applications.

However, these benefits come at a cost. Heterogeneous systems incur greater non-recurring engineering (NRE) effort, higher communication overhead, and increased memory bandwidth contention—factors that limit scalability and adoption. A primary contributor is inefficient communication among heterogeneous components. Specifically, mismatched I/O interfaces hinder reusability and drive up NRE; poor latency tolerance creates performance bottlenecks; and inadequate resource allocation leads to contention and interference. These challenges arise at multiple stages of system design and collectively slow or block deployment in real-world scenarios.

This dissertation presents minimally invasive solutions that streamline heterogeneous system design by directly addressing these communication challenges. First, it introduces Twine, a design language for heterogeneous design that standardizes communication interfaces and automates control logic generation. Twine reduces design specification size by 3×, enhancing reusability and reducing engineering overhead. Second, it proposes Zipper, a set of latency-tolerant bus optimizations that enable systems to tolerate microsecond-level delays without drastic redesign. By exploiting the temporal locality and parallelism that exist in applications, Zipper delivers up to 8× performance gains. Finally, it introduces Overpass, a flexible interconnect system with distributed resource allocation that optimizes bandwidth utilization. Overpass increases system performance by 35%, enabling efficient communication across diverse components.

Together, Twine, Zipper, and Overpass complement each other, forming a cohesive framework to help developers address the core communication bottlenecks of heterogeneous hardware at various design stages. These solutions help developers extract greater performance from their designs while conserving valuable engineering effort. By directly addressing the fundamental barriers to adoption, this dissertation advances the practicality and effectiveness of heterogeneous system design and lays the groundwork for broader deployment and continued innovation in the field.

Details

1010268
Title
Streamlining High-Performance Heterogeneous Hardware Design
Number of pages
152
Publication year
2025
Degree date
2025
School code
0127
Source
DAI-B 87/2(E), Dissertation Abstracts International
ISBN
9798291566244
Committee member
Jeannin, Jean-Baptiste; Bertacco, Valeria M.; Tzimpragos, Georgios
University/institution
University of Michigan
Department
Computer Science & Engineering
University location
United States -- Michigan
Degree
Ph.D.
Source type
Dissertation or Thesis
Language
English
Document type
Dissertation/Thesis
Dissertation/thesis number
32271806
ProQuest document ID
3245431776
Document URL
https://www.proquest.com/dissertations-theses/streamlining-high-performance-heterogeneous/docview/3245431776/se-2?accountid=208611
Copyright
Database copyright ProQuest LLC; ProQuest does not claim copyright in the individual underlying works.
Database
ProQuest One Academic