Research on new low power integrated circuit design method

Abstract

Conference Title: 2025 5th International Conference on Electronics, Circuits and Information Engineering (ECIE)

Conference Start Date: 2025 May 23

Conference End Date: 2025 May 25

Conference Location: Guangzhou, China

Aiming at the problems of high power consumption and poor flexibility of traditional single voltage domain design methods, this paper proposes a new low-power integrated circuit design method based on multi-voltage domain division and layout optimization. The study first starts with the causes of power consumption and the principles of mainstream low-power technology, and systematically sorts out the modeling mechanisms of dynamic power consumption, static power consumption and short-circuit power consumption; in the design stage, power consumption-aware modeling, multi-voltage domain module division, voltage isolation unit configuration and layout optimization strategies are adopted, and the UPF standard is combined to realize automatic process configuration; in the verification stage, based on the 2024 AICircuit dataset, a complete experimental platform is built to complete the functional verification, power consumption test and performance evaluation of the test chip. The experimental results show that compared with the traditional design method, the new method can achieve a dynamic power consumption reduction of about 18%, a static power consumption reduction of about 17%, and an area optimization improvement of about 8%. This study provides a feasible engineering implementation path for low-power integrated circuit design, and also lays the foundation for the development of intelligent power management methods in the future.