Design and Analysis of Low Power and High-Speed FIR Filter Using Advanced Optimization Techniques

Abstract

Conference Title: 2025 6th International Conference for Emerging Technology (INCET)

Conference Start Date: 2025 May 23

Conference End Date: 2025 May 25

Conference Location: BELGAUM, India

This project involves designing and analyzing low power, high speed FIR filter using advanced optimization techniques such as feed forward cutset design and pipeline retiming design for its implementation. The above technique aims to optimize the consumption of power in the system by improving the system’s performance and offering thermal stability. Analysis done at first has shown that total power dissipated within the chip is 35.064 W and has been causing unsafe junction temperatures of 91.0 °C. When pipeline retiming and feed-forward cutset design optimization techniques were used, then it solved the problem, reduced total on-chip power to 27.527 W, thus decreased junction temperature down to 76.6 °C, therefore providing thermal stability as well as reliability. Resource utilization analysis infers that there is effective utilization of FPGA resources. All the prime modules, like Flip-Flops that are FDCE, Arithmetic Blocks like DSP48E1, and LUTs, were optimized to the maximum extent. In pipeline designs, multi-stage processing with balancing feedback paths highly improves the performances and also leads to a noteworthy reduction in terms of power efficiencies. The proposed FIR filter design appears to be a power-efficient and high-speed solution to many modern applications in the digital signal processing field. The hereby presented method allows proper thermal management combined with optimum use of hardware resources, which has rather high computation throughput. Thus, it is also possible to realize digital systems efficiently.