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© 2025 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.

Abstract

Time synchronization is critical for task-oriented and time-sensitive Industrial Internet of Things (IIoT) systems. Nevertheless, achieving high-precision synchronization with low communication overhead remains a key challenge due to the constrained resources of IIoT devices. In this paper, we propose a single-timestamp time synchronization scheme that significantly reduces communication overhead by utilizing the mechanism of AP to periodically collect sensor device data. The reduced communication overhead alleviates network congestion, which is essential for achieving low end-to-end latency in synchronized IIoT networks. Furthermore, to mitigate the impact of random delay noise on clock parameter estimation, we propose a noise-robust-based Maximum Likelihood Estimation (NR-MLE) algorithm that jointly optimizes synchronization accuracy and resilience to random delays. Specifically, we decompose the collected timestamp matrix into two low-rank matrices and use gradient descent to minimize reconstruction error and regularization, approximating the true signal and removing noise. The denoised timestamp matrix is then used to jointly estimate clock skew and offset via MLE, with the corresponding Cramér–Rao Lower Bounds (CRLBs) being derived. The simulation results demonstrate that the NR-MLE algorithm achieves a higher clock parameter estimation accuracy than conventional MLE and exhibits strong robustness against increasing noise levels.

Details

Title
Noise-Robust-Based Clock Parameter Estimation and Low-Overhead Time Synchronization in Time-Sensitive Industrial Internet of Things
Author
Tang, Long 1   VIAFID ORCID Logo  ; Li Fangyan 1   VIAFID ORCID Logo  ; Yu Zichao 2   VIAFID ORCID Logo  ; Zeng Haiyong 1   VIAFID ORCID Logo 

 Guangxi Key Laboratory of Braininspired Computing and Intelligent Chips, School of Electronic and Information Engineering, Guangxi Normal University, Guilin 541001, China; [email protected] (L.T.); [email protected] (F.L.) 
 Department of Electronic Engineering and Information Science, University of Science and Technology of China, Hefei 230022, China; [email protected] 
First page
927
Publication year
2025
Publication date
2025
Publisher
MDPI AG
e-ISSN
10994300
Source type
Scholarly Journal
Language of publication
English
ProQuest document ID
3254508944
Copyright
© 2025 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.