Design and Verification of Low Latency AMBA AXI4 and ACE Protocol for On-Chip Peripheral Communication

Abstract

The expeditious development of the technologies result in immeasurable growth in Integrated Circuit chips. The on-chip communication description plays a major role in connection and management of the functional blocks of the system on chip. The Advanced eXtensible Interface (AXI) and AXI Coherence Extension are the two protocols introduced in the later version of AMBA. AXI4 is the high speed bus which has five channels for write and read operation with handshaking mechanism for control transmission. ACE have three channels in addition to the existing channels in AXI4 for cache coherence. This work focuses on the design and analysis of AXI4 and ACE protocols using Verilog language and test bench environment with help of the system Verilog environment. The functional verification of AXI and ACE interconnects, simulation waveforms developed using Cadence Xcelium EDA (Electronic Design Automation) tool and explored as per expectation without any change in the features of DUT (Design Under Test).The design is verified for both 16 bytes and 256 bytes per transfer providing 4 transfers and 4 bytes per transfer for transferring 16 bytes in a single transaction and providing 16 transfers and 16 bytes per transfer for transferring 256 bytes in a single transaction. Thus, the work shows that ACE protocol supports the snooping concept additionally to overcome cache coherence problem along with the features of AXI protocol. The environment completely encloses the DUT while monitoring those protocol's performance. The key benefit of creating a system Verilog testbench is that verification engineers will spend less time in verifying the design since the testbench is reusable. The features of this protocol help in improving the bandwidth and latency of data transfers and transactions during the communications between the peripherals.