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Over the last few decades, electronic devices have become ubiquitous across all sectors, as their evolution has been rapid, particularly in the prevalent adoption of System-on-Chips (SoCs). With the potential end of Moore’s and Dennard’s laws, an alternative strategy has been proposed to enhance both functionality per area and yield via packaging segregated functionality dies on a common interposer die, known as a System-in-Package (SiP). With the growth of chiplets, interposers and SiP integration processes, a novel distributed supply chain manifests itself, which contains multiple chiplet developers and foundries, introducing vulnerabilities. With chiplets being sold on an open market, verification of their origin and authenticity is challenging. Lack of control at various stages of the supply chain increases counterfeit threats at chiplet, interposer, and SiP levels. This dissertation pinpoints SiP supply chain threat models while classifying SiP counterfeit threats and developing mitigation strategies. This work includes the development of a blockchain framework to detect counterfeit SiPs, the development of a prototype HI-Chain and the expansion of the framework, and the development of a hardware-based technique, the Heterogeneous Integration-Secure Split Test (HI-SST), that targets specific counterfeit threats. As a vital component of the work, the Chiplet Hardware Security Module (CHSM) and the Chiplet Security IP (CSIP) are utilized to establish trust. Various evaluations and simulations were also leveraged as the supply of test counterfeit SiPs/benchmarks in addition to a readily available CHSM is scarce.