Design of JESD204B Receiving Circuit in a 4Gsample/s 12Bit DAC

Abstract

Conference Title: 2025 4th International Symposium on Semiconductor and Electronic Technology (ISSET)

Conference Start Date: 2025 July 24

Conference End Date: 2025 July 26

Conference Location: Xi'an, China

To address the challenges of design complexity and low feasibility in data receiving circuit design of 4 Gsps 12 Bit Digital-to-Analog Converter (DAC), a receiving circuit conforming to JESD204B protocol is designed in this paper. The physical layer of the circuit is completed by Gigabit Transceiver (GTX) IP core. The link layer adopts the four-byte parallel processing structure, reduces the system clock requirement from 1 GHz to 250 MHz and proposes the use of a four-byte data adjustment function to align tail position of multi-frame, which is convenient for frame data processing. The transport layer restores the frame data at the link layer to the sampled data. On the Field Programmable Gate Array (FPGA) platform, the JESD204B sender IP core is invoked to simulate the sender to send data, and the receiving circuit is jointly verified. The experimental results show that the circuit complies with the JESD204B receiving protocol, meets the data receiving requirements of 4 Gsps 12 Bit DAC and occupies less resources than single-byte and double-byte design schemes under the same processing effect.