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The growing complexity of Application-Specific Integrated Circuits (ASICs) has driven the demand for more efficient design and verification methodologies. This thesis explores a range of techniques and toolchains that span the full ASIC flow from register-transfer level (RTL) design and verification to layout generation and security evaluation.
We begin with the design of functional RTL components such as finite-state machines (FSMs), matrix multipliers, an Advanced High-Performance Bus (AHB) to SRAM controller, and a small neural network accelerator. We establish functional correctness through simulation (Synopsys VCS with Verdi), functional and code coverage, and selected formal checks. For physical design, we demonstrate RTL-to-GDSII using OpenLane with the Sky130 PDK and perform logic synthesis and timing analysis via Synopsys Design Compiler, reporting configuration choices and the resulting area and timing for our designs.
We then review applications of machine learning in hardware design and verification, with emphasis on large language model (LLM)-assisted methods. In our work, LLMs are applied to module-level verification support, including automatic generation of testbenches and checkers.
Finally, we present real-world case studies in hardware security, centered on vulnerabilities in the OpenTitan SoC platform. Using formal tools (VC Formal, SpyGlass), taint tracking, and custom bug-detection scripts, we uncover security flaws and propose automated mitigation workflows.
Together, these contributions demonstrate a comprehensive methodology for secure, verifiable ASIC design using both traditional and AI-augmented toolchains.