Content area
The advent of nanotechnology has significantly influenced the development of advanced transistor architectures, such as the Junctionless Field Effect Transistor (JLFET). Among various designs, mainly surrounded channel Junctionless field effect transistor (SCJLFET) is a structure without junction where the gate is placed inside the body of the device or in other words the gate is surrounded by the channel region. In a device based on MOS structure the most important parameter is the threshold voltage. This paper presents a comprehensive analytical method for determining the threshold voltage (Vth) of the surrounded channel Junctionless FET (SCJLFET). For a Junctionless field effect transistor (JLFET) the thresh-old voltage can be explained as the maximum value of gate voltage at which the value of the depletion width exactly equals to the thickness of the Si region. If the value of the gate voltage is above the value of the threshold voltage, the depletion width value is less than the thickness of the Si region then the device is turned on. The threshold voltage model for double gate JLT has also been obtained from the depletion width model. In this paper it is presented that the novel model SCJLFET exhibits much better characteristics compared to other conventional structure, incorporating key design parameters such as channel length, work function, drain voltage, gate oxide thickness, dielectric constant of gate dielectric and temperature. The threshold voltage model has been simulated in MATLAB simulation environment. Result obtained in the simulation work in MATLAB has been compared with the simulation result obtained from TCAD.