Q2SV: A High‐Level Synthesis Approach for State Vector Quantum Simulation

Abstract

This study presents Q2SV, an FPGA‐based quantum state vector simulator implemented using high‐level synthesis (HLS), capable of simulating quantum circuits with up to 29 qubits. Using FPGA parallelism, efficient memory allocation, and hardware‐optimized execution pipelines, Q2SV achieves scalable quantum simulation without requiring iterative resynthesis. The system’s workflow processes OpenQASM circuits by providing a flexible and general‐purpose quantum state vector simulation approach. Experimental evaluations demonstrate significant reductions in execution time and storage requirements, positioning FPGAs as a possible alternative to GPUs and CPUs for large‐scale quantum circuit emulation. While not yet matching the raw computational power of high‐end CPUs and GPUs in all cases, this work establishes a foundational framework for future optimizations in hardware‐accelerated quantum simulation. This work provides an adaptable HLS‐based code that serves as a template that paves the way for enhanced memory management, parallel processing, and architecture‐specific optimizations, enabling more efficient FPGA‐based quantum simulations in the future.