Scaleable Multichannel Square‐Wave Sequence Generator Based on the RP2040 Microcontroller

Abstract

ABSTRACT

Multichannel signal generators are used in many fields of science. For example, they are used to drive ultrasonic phased arrays and usually employ FPGAs or DSPs. We present a design based on the synchronization of multiple low‐cost RP2040 microcontrollers to generate digital square wave signals (PWM) with a granularity of $$4 \,\mathrm{n}\mathrm{s}$$. Due to its modular design, the device is directly scalable to an arbitrary number of output signals. The CPU clocks are synchronized, and PIO modules are used to generate synchronized interrupts across the system. This ensures a stable phase relation across all output signals with a remaining jitter of $$0.17 \,\mathrm{n}\mathrm{s}$$. We demonstrate the generation of chirp signals by utilizing the DMA for hardware‐level data transfer. This signal generator can be utilized, for example, to control ultrasonic phased arrays and to generate arbitrary test patterns for digital circuits.

Introduction

Multichannel signal generators are necessary in many fields of science. They have found particularly wide application in the field of ultrasound for controlling phased arrays of transducers [1]. They should provide signals for each channel with an adjustable amplitude and phase relation with a typical frequency range from 1 MHz to 10 MHz. Usually, such generators use field programmable gate arrays (FPGA) or digital signal processors (DSP) [2–4], which are often expensive for low-channel arrays, and difficult to operate and maintain particularly in laboratories without special competence. As high-speed microcontrollers became available, people began to use them for arbitrary digital signal generation [5, 6].

We have applied a cost-effective solution for multichannel generation of arbitrary digital signals by combining several Raspberry Pi Pico modules [7] based on the RP2040 chip [8]. Each chip can provide eight separately controlled pulse width modulation (PWM) channels. The system can be scaled by synchronizing multiple chips to increase the number of channels. The low cost of components and scalability allows it to be used in cost-sensitive applications that benefit from a large number of channels.

Materials and Methods

Figure 1 shows the schematic of the system. Figure 2 shows an early prototype board, which was later extended into a system consisting of 8 RP2040 chips on a dedicated PCB. The prototype board features two Raspberry Pi Pico modules. One is operated as the primary module, which generates the reference clock and communicates with the control computer via USB. It forwards instructions to the secondary module(s) via a unidirectional serial interface. An individual address, comprising a 3-bit binary number, is assigned to each Raspberry Pi module using the address pins (ADR2, ADR1, ADR0 in Figure 1). Each address pin uses the internal pull-up resistor and can be programmed by connecting it to the ground (binary value 1) or left unprogrammed by keeping the pin floating (binary value 0). This allows to address up to 8 modules for 64 channels in total.

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The CPUs are overclocked to 248 MHz. This results in a clock cycle of 4 ns, which defines the time granularity of the signals.

Clock Synchronization

The CPU clocks of the individual modules are synchronized to keep the generated signals in phase-lock. This is done with the 12 MHz reference oscillator signal from GP21 [8, Section 2.15.3] of the primary module. This signal is fed into the XIN pin of the secondary module(s) and used as the reference for the internal phase-locked loop (PLL) oscillator generating the $$248 \,\mathrm{M}\mathrm{Hz}$$ CPU clock. The function of the XIN pin is described in [8, Section 2.16]. The modification is done by removing the on-board quartz and the load capacitors and using the exposed pads to connect the 12 MHz signal. By this modification, all CPUs use the same clock reference and run in phase-lock.

When setting up, care must be taken to first program the primary module and enable the output of the 12 MHz signal, which is mandatory for booting the secondary modules.

Interrupt-Controlled Start

We use the integrated PWM channels [8, Section 4.5] to generate the output signals. They can be started simultaneously for each module, enabling phase control between channels. The naive approach uses an external interrupt (falling edge) to synchronize the startup between multiple modules. The enable signal is generated by the primary module GP18 and fed to GP19 of each module, although an external signal could also be used. All modules use the same interrupt routine to ensure equal startup time.

This approach is only satisfactory if the execution of the interrupts is not delayed either by waiting for the system to finish other service routines (e.g., related to the USB interface) or waiting to access the memory or the periphery. To mitigate this problem, the interrupt service routine is assigned to the second CPU core (core1), where only the interrupt related to the start is handled. The code is moved to the scratch Y memory space [8, Section 2.6.2] by using the modified function declaration

void __scratch_y("core1") ISR_function().

Also, the bus priority is set to core1 [8, Section 2.1.1.1].

Reference Clock Controlled Start

To realize a fully synchronized start, a programmable input-output (PIO) module [8, Section 3] is used to output a symmetric 1 MHz square wave signal and generate an internal interrupt. The interrupt is generated at a precise moment and in fixed relation to the square wave signal. The software can adjust the phase of the signal. Aligning the signals of all modules ensures that the interrupts are generated simultaneously across the entire system. This interrupt then checks if the start condition is met and enables the signal output.

An exclusive-OR (XOR) gate (74HC86 [10]) is used to automate signal alignment by comparing the phase of the 1 MHz square wave of the primary module to that of one secondary module. If the square waves are in phase, a constant low value is output from the gate. In the case of phase deviation, a high signal pulse is generated with a duration that is proportional to the phase mismatch. A maximum duration is reached at $$180^{\circ }$$ phase delay, generating a constant high signal.

A peak detector enhances the detectability of small phase deviations. The circuit is shown in Figure 1 and formed by a small-signal diode (1N4148 [11]), a capacitor ($$33 \,\mathrm{n}\mathrm{F}$$) and a discharge resistor ($$68 \,\mathrm{k}{\Omega}$$).

The output signal of the peak detector is fed into the secondary module's analog-to-digital-converter (ADC) (GP26) [8, Section 4.9]. Automatic synchronization is achieved with a firmware function that adjusts the phase until the ADC output reaches a minimum. This phase alignment is carried out whenever the system is powered up, after which all modules remain synchronous.

Continuous and Gated Burst Mode

The integrated PWM modules [8, Section 4.5] are directly used for continuous and burst mode operation. They are preconfigured with a desired initial phase, duty cycle, and signal period. The interrupt activates the PWM modules simultaneously, and once the enable signal ends the PWM modules are stopped, and the values are reinitialized.

Chirp Mode

For chirp mode, the direct memory access (DMA) system [8, Section 2.5] is used. The 12 DMA channels transfer data from the memory to the PWM modules independent of the CPU. Two separate DMA channels are used to transfer the period and duty cycle values. This allows the control of 6 PWM outputs. The data is stored as 16-bit values in the memory. Therefore, for each segment and each PWM output, 4 bytes need to be stored.

The benefit of chirp mode is that arbitrary square wave sequences can be generated. The sequence is defined by segments where a high signal of $$n_{high}$$ clock cycles is followed by a low signal of $$n_{low}$$ clock cycles. The period of the PWM is set to $$n_{high}+n_{low}$$ and the duty cycle to $$n_{high}/(n_{high}+n_{low})$$. Segments of up to $$264 \,\umu \mathrm{s}$$ can be realized using the full range of the 16-bit values. One limitation is that $$n_{high}+n_{low}$$ must constitute enough clock cycles for all DMA channels to access the memory and update the PWM settings before the start of the next segment.

A slight modification of the chirp mode is to operate at a fixed PWM frequency and use 8 DMA controllers to update only the duty-cycle values of the 8 PWM controllers. This enables the amplitude control of bursts, reduces memory consumption, and ensures that all eight channels per chip can be utilized.

PWM Filtering

According to the Fourier theorem, any periodic signal can be described as a superposition of sinusoidal signal components. In usual applications—for example, digital-to-analog converters—a low-pass filter extracts the near DC signal components to form an analog signal.

In our ultrasonic application, we feed the PWM square wave signal to a single MOSFET for amplification [12]. A subsequent band-pass filter isolates the fundamental frequency equal to the PWM frequency, converting the square wave signal into a sinusoidal signal.

Results

Duty Cycle and Phase Control

Control of the duty cycle and phase is implemented as specified in the RP2040 datasheet [8]. The PWM signal frequency 1 $$$\begin{equation} f_{PWM} = \frac{f_{CPU}}{n} \end{equation}$$$is an integer fraction $$n$$ of the CPU frequency1 $$f_{CPU}=248\, {\rm MHz}$$. $$n$$ is also the number of clock cycles in one signal period. The duty cycle can be adjusted in increments of $$100\%/{n}$$ and the phase in increments of $$360^{\circ }/{n}$$. This implies that the amplitude and phase resolutions are discrete and reduced with increasing PWM frequency. Figure 3 shows an output signal from the PWM module for each operation mode: a 2 MHz continuous square wave signal, a burst signal, and a chirp signal with a limited number of cycles.

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Jitter and Synchronization

The signal jitter between different modules was evaluated. The data of 10 000 repeated starts was recorded with a LeCroy HDO6104 oscilloscope, and the start time deviation was analyzed using the integrated statistics function.

In interrupt mode, a deviation of several clock cycles was observed. This is because the edge is not steep enough to be reliably detected.

Using the synchronized reference clock generates an interrupt with clock cycle precision. Using this interrupt to start the signal generation ensures phase synchronization across modules on the clock cycle level. The remaining jitter of the signal (full width at half maximum) is 0.17 ns. This is far below 4 ns, the period of one clock cycle.

Chirp Generation

A linear chirp signal with a start frequency of 2 MHz and an end frequency of 3 MHz was generated. The chirp duration was $$200 \,\umu \mathrm{s}$$, comprising 500 cycles, and occupied 2000 bytes of memory per channel (16-bit values for both the duty cycle and the duration of each cycle). One dataset of the digital PWM signal was recorded with the LeCroy HDO6104 oscilloscope. The short-time Fourier transformation of the signal is shown in Figure 4, which shows the linear time-frequency relation. The digitally filtered signal (the bandwidth frequency range is from 1.5 MHz) to 3.5 MHz is also presented to demonstrate amplitude modulation of the chirp.

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Chirp mode can also be used to generate multiple-cycle delays between channels, and to generate arbitrary pulse sequences. The maximum number of cycles per burst is determined by the amount of available memory. Sequences with 1000 cycles (per channel) have been successfully tested, requiring 24,000 bytes of memory in total.

Discussion

Synchronization across the modules was shown to be accurate and stable over time, enabling reliable phase-controlled multichannel signal generation. Furthermore, the presented design is directly scalable by introducing more secondary modules. The presented design features low hardware costs (under one dollar per output channel), making it a cost-effective and easy-to-operate alternative to traditional signal generators or FPGAs. Our straightforward design also addresses the high initial development requirements of special purpose systems, which are often manufactured only in low volumes.

The phase and duty cycle resolutions depend on the working frequency in relation to the CPU frequency. As an example, operating at a frequency of 2 MHz, the phase can be adjusted in 124 steps with $$2.9^{\circ }$$ increments. The theoretical maximum frequency would be 124 MHz, with a limited set of only two phase values ($$0^{\circ}$$ and $$180^{\circ}$$).

Each module relies on an internal PLL oscillator to generate the main CPU clock. These PLLs are synchronized using the external 12 MHz crystal oscillator, but each PLL has an independent drift which can be seen as a jitter between the signals originating from different modules. This jitter was found to be $$0.17 \,\mathrm{n}\mathrm{s}$$, which is reasonably small compared to a single clock cycle of $$4 \,\mathrm{n}\mathrm{s}$$ and is certainly acceptable for many applications. Signals originating from the same module show an even lower jitter.

In chirp mode, the maximum signal frequency is limited by the time taken for the DMA system to update the values of the PWM channels. During each clock cycle, only one DMA transfer can be executed; 12 clock cycles are required to process all 12 DMA transfers, imposing a theoretical maximum frequency of $${f}_{\max}={f}_{\textit{CPU}}/12\approx 20\,\mathrm{MHz}$$. A safety margin should be included, as other systems may request RAM access and postpone the next DMA transfer. If the value of the PWM module cannot be updated before the end of the ongoing cycle, the previous cycle's settings will repeat. One option to increase the maximum frequency is to reduce the number of active DMA channels and, therefore, the number of active outputs per controller.

In the presented design the clock systems of the secondary controllers were manually modified by replacing their oscillators with the 12 MHz oscillator signal from the primary controller. While appropriate for prototyping, it would be preferential to design a dedicated printed circuit board using individual components. For larger systems, this would further reduce system costs and minimize manual labour. Furthermore, a stand-alone oscillator and clock distribution system could be designed where the same reference clock feeds all controllers.

Instability of the enable signal amplitude increases the risk that some controllers might read an incorrect state, which would cause the start of the signals to be delayed by an entire period of the 1 MHz reference clock. Although this can be mitigated by checking the signal state repeatedly before the signal output is activated, the collective start time would be delayed.

An alternative approach is to use the reference clock output signal and its deterministic relation when the interrupt service routine evaluates the signal state. This allows monitoring of the critical region where the signal must be stable and no transition should occur. A simple automated solution would be to gate the enable signal by a D flip-flop. The flip-flop is controlled by the reference clock output. The timing of the interrupt generated by the PIO program must be carefully aligned such that the signal evaluation by the interrupt service routine takes place when the flip-flops hold the signal level stable.

One limitation of the presented design is that the band-pass must be specifically designed to the required operation frequency. In addition, the frequency range for a chirp signal is limited by the condition that, for low-frequency signals ($$f_{low}$$), the second harmonic ($$2\cdot f_{low}$$) should be sufficiently suppressed by the band-pass. However, this condition implies that a possibly desirable high-frequency signal with $$f_{high}=2\cdot f_{low}$$ will also be suppressed.

Conclusion

We present a multichannel PWM signal generator based on the Raspberry Pi Pico module and the RP2040 chip. It synchronizes multiple chips to realize a scalable design. It can generate burst and chirp signals with adjustable duty cycles and periods.

The start of the signal can be synchronized with an external interrupt, which results in a phase jitter between modules over several clock cycles. Steady performance was achieved by using a synchronized reference timer to control the start of the burst.

The output square wave signal can be converted to a sine wave signal by isolating the fundamental frequency with a band-pass filter. The signal can also be used to drive power amplifiers [12] to generate high-power signals for ultrasonic transducers.

Author Contributions

Martin Weber: conceptualization, formal analysis, software, visualization, writing – original draft. Jere Hyvönen: conceptualization, investigation, resources, validation, visualization, writing – review & editing. Dmitry Nikolaev: conceptualization, writing – review & editing. Edward Hæggström: supervision, writing – review & editing. Ari Salmi: funding acquisition, supervision, writing – review & editing.

Acknowledgements

The authors thank summer intern Louan Bandeira for working on synchronizing the modules during his internship. The authors thank Topi Pudas for refining the language in the manuscript. Funding was provided by the Research Council of Finland (Grants 347459 and 349200). The Helsinki University Library funded open access.

Conflicts of Interest

The authors declare no conflicts of interest.

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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