Harnessing chaotic bifurcation in positive feedback transistors for secure and scalable random key generation

Abstract

In the era of big data, robust data security is more critical than ever. One promising way to create unpredictable random keys is to use the intrinsic physical randomness of electronic devices. However, controlling and reproducing this randomness remains a significant challenge. For the first time, we reveal a parabolic input-output relationship enabled by the band-to-band tunneling (BTBT) mechanism in a positive feedback transistor (PFT). By applying iterative operations, we observe chaotic bifurcation behavior, which allows the stable generation of analog random values across more than 10¹⁰ cycles. These random values are then used to encrypt and decrypt images, showcasing how encryption technologies can be implemented with just a single PFT. We also show that the charge-trap flash memory (CTF) array integrated with the PFTs can store encrypted information. This study highlights the potential of PFTs as random key generators and examines the device’s behavior under chaotic conditions. By leveraging the physical characteristics of the device, we provide a secure and reliable method for data encryption.

True random number generators are highly demanded for secured data processing, yet it remains challenging to control and reproduce the randomness. Im et al. generate analog random values using a positive feedback transistor and implement it to encrypt and decrypt images, and store encrypted information.

Introduction

In the era of big data, the rapid growth of diverse and voluminous datasets−from financial transactions to healthcare records—demands advanced methods for secure and efficient data processing^{1, 2–3}. Biometric information, which includes sensitive data such as fingerprints and iris patterns, has become a key part of various applications, from personal authentication systems to national security frameworks^{4, 5–6}. Due to the sensitivity and critical nature of these data, strong security measures are essential to prevent unauthorized access and breaches.

Traditional encryption algorithms, such as the advanced encryption standard (AES)⁷, Rivest-Shamir-Adleman (RSA)⁸, and elliptic-curve cryptography (ECC)⁹, have long served as the foundation of data security, providing strong cryptographic protections. However, these algorithms are computationally intensive by nature, as they depend on complex mathematical operations that lead to significant computational overhead and resource consumption. This not only restricts their scalability but also creates challenges for implementation in resource-constrained environments, such as embedded systems and Internet of Things (IoT) devices.

To address these challenges, alternative approaches leveraging physical phenomena for random key generation have gained attention. Quantum key distribution (QKD)^{10, 11–12} and true random number generators (TRNGs) based on the stochastic behavior of electronic devices, such as resistive random-access memory (RRAM) threshold switching^{13, 14–15}, exemplify this shift. These physical methods exploit the inherent unpredictability of quantum processes or device-level randomness to generate secure encryption keys, which strengthens data security. However, despite their potential, these approaches face significant limitations. QKD, while offering unparalleled security, requires costly and complex infrastructure, including specialized optical fibers and single-photon detectors, which restricts its large-scale deployment^{16, 17, 18–19}. In addition, the restricted transmission distances that are inherent to QKD further constrain practical applications^20,21.

RRAM-based TRNGs offer a more scalable alternative by utilizing the intrinsic stochastic properties of electronic devices to generate random numbers efficiently. However, the reliability and consistency of these TRNGs often suffer due to device variability, environmental fluctuations, and process-induced inconsistencies, which can weaken the robustness of the generated random keys^{22, 23–24}. These limitations highlight the need for novel approaches that combine the benefits of physical random key generation with improved stability and scalability. Magnetic tunnel junction (MTJ)-based TRNGs have also been widely reported^{25, 26–27}. MTJs exploit thermally activated stochastic magnetization switching under spin-transfer or spin-orbit torque, and have demonstrated excellent endurance and ultrahigh throughput, exceeding the gigabit-per-second regime^28,29. While these results highlight the potential of MTJs as highly efficient entropy sources, MTJ-based TRNGs also suffer from magnetic crosstalk and device-to-device variability as well as temperature-dependent switching bias, which can degrade randomness quality and robustness under varying conditions^30,31.

In this context, we propose a novel technique that harnesses the band-to-band tunneling (BTBT) mechanism in fabricated positive feedback transistors (PFTs) to achieve stable and scalable analog random number generation. The proposed method exploits the chaotic bifurcation behavior inherent in PFTs, which enables the generation of stable analog random numbers that are suitable for secure encryption applications. While the initial conditions ideally determine chaotic bifurcation, the inherent variability in device characteristics introduces significant unpredictability into the process. This unpredictability leads to the generation of truly random and non-deterministic values. In addition, this mechanism depends on the read operation in the PFT instead of relying on program/erase variability. As a result, the generation of numerous outputs does not degrade the device, which improves its reliability and longevity.

Figure 1a, b shows the 3-D schematic of PFT, a scanning electron microscopy (SEM) image, and a transmission electron microscopy (TEM) cross-sectional view of the fabricated PFT, respectively. The structure of the PFT comprises a p-doped floating body and an n-doped floating body situated between an n⁺-doped cathode and a p⁺-doped anode. Each floating body is independently modulated by two gates (gates 1 and 2), separated by a SiO₂/Si₃N₄/SiO₂ (ONO) insulating layer, which enables precise control over the electrical characteristics.

Fig. 1 Random-number generation process using the PFTs. [Images not available. See PDF.]

a 3-D Schematic of PFT. b SEM, and (c) TEM cross-sectional images of the fabricated PFT. d Proposed random number generation process utilizing the PFT. e Image encryption using the generated random numbers from the PFT as the encryption key. Encryption and decryption can be performed using the XOR operation.

The random number generation process with the PFT is shown in Fig. 1d. By modulating the voltage applied to gate 2 (V_G2), the threshold voltage required at gate 1 (V_G1,on) for activating the PFT is adjusted dynamically, which leads to a parabolic relationship between V_G1,on and V_G2. By iteratively scaling V_G1,on by a factor (α) and feeding it back as the input to V_G2, the system generates random V_G1,on values characterized by the specific α. These randomly generated V_G1,on values act as secure encryption keys for data protection. Figure 1e illustrates the practical application of this process through the encryption and decryption of fingerprint images using an XOR operation with the PFT-generated random keys. Experimental results confirm the reliable generation of stable random numbers from the PFT and validate the effectiveness of these keys in successfully encrypting and decrypting biometric data.

Our approach overcomes the limitations of existing physical random key generation methods by providing a scalable and stable solution that takes advantage of the inherent properties of PFTs. The stable and infinitely repeatable operation of a single PFT, combined with chaotic bifurcation behavior, ensures robust randomness. At the same time, the device structure allows seamless integration into conventional semiconductor technologies, which paves the way for practical and secure encryption systems. This advancement highlights the potential of using physical mechanisms to enhance data security in the rapidly growing field of big data and biometric applications.

Results

Electrical characteristics of PFTs

We monolithically integrated the PFTs with CMOS transistors and charge-trap flash (CTF) memory cells on a six-inch silicon-on-insulator (SOI) wafer. The detailed fabrication process is described in Supplementary Fig. 1. The SOI wafer was used instead of a bulk Si wafer to form floating bodies for stable charge accumulation, which is essential for positive-feedback operations³². At zero bias, junction barriers at both floating-body interfaces impede carrier injection, and the PFT remains off as depicted in Fig. 2a. Increasing the bias of the G1 (V_G1), with a forward bias at the anode (V_A), injects electrons into the n-doped floating body. The resulting electrostatic shift lowers the anode-side barrier and promotes hole injection into the p-doped floating body. This reciprocal modulation of the two barriers establishes a positive-feedback pathway, yielding an abrupt increase in anode current (I_A) once V_G1 surpasses the certain threshold (V_G1,on), as shown in Fig. 2b. With the positive bias on the G2 (V_G2), the energy band of the n-doped floating body shifts downward, elevating the anode-side barrier and refraining the positive-feedback. Consequently, V_G1,on is increased as illustrated in Fig. 2c.

Fig. 2 Operating mechanism of the PFT. [Images not available. See PDF.]

a initial state, (b) turn-on condition, (c) application of a positive V_G2, and (d) application of a large V_G2. I_A-V_G1 transfer curves as a function of V_G2, ranging from (e) 0 V to 0.9 V and (f) 1 V to 2.2 V. g Parabolic relationship between V_G1,on and V_G2.

When V_G2 increases beyond a specific value, a different phenomenon occurs. As shown in Fig. 2d, when a large V_G2 is applied, the energy band between the p-doped floating body and the n-doped floating body (as well as between the n-doped floating body and the anode) becomes thinner. This process allows electrons in the valence band of the p-doped body and the anode to move to the conduction band of the n-doped body via BTBT. Hence, electron-hole pairs (EHPs) are generated, which raises the energy band of the n-doped floating body and causes positive feedback to occur with lower V_G1,on. The occurrence of BTBT under high V_G2 bias was further validated through Sentaurus TCAD device simulations (Supplementary Fig. 2). The simulation results clearly demonstrate that a higher V_G2 increases the generation of EHPs.

The occurrence of BTBT at high V_G2 is also experimentally observed in the electrical measurements of the PFT. Figure 2e shows the I_A-V_G1 transfer curve with various V_G2 ranging from 0 V to 0.9 V. When V_G1 exceeds a specific V_G1,on, the I_A increases rapidly (via positive feedback), which indicates ultra-steep switching. As V_G2 increases, the energy barriers encountered by holes at the anode become higher, leading to an increase in V_G1,on. In contrast, as shown in Fig. 2f when V_G2 increases from 1 V to 2.2 V, BTBT occurs, causing V_G1,on to decrease gradually. As a result, the relationship between V_G2 and V_G1,on exhibits a parabolic shape as depicted in Fig. 2g. Note that the PFT switches with a very steep subthreshold swing (SS) of less than 1 mV/decade.

Chaotic bifurcation in PFTs

The parabolic relationship between V_G1,on and V_G2 is analogous to the logistic map, which is known to exhibit unpredictable chaotic behavior under certain conditions³³. Building on this, we experimentally validated whether chaotic outputs can be achieved in PFTs. Repetitive V_G1,on values are generated by iteratively feeding back a V_G2 that is proportional to the obtained V_G1,on. The equation governing the calculation of the next input V_G2 from the current V_G1,on is defined as follows:

1

$$V_{\mathrm{G}2}^N=\alpha \times \left(V_{\mathrm{G}1,\mathrm{on}}^{N-1}-V_{\mathrm{base}}\right)$$

2

$$V_{\mathrm{G}1,\mathrm{on}}^N=f\left(V_{\mathrm{G}2}^N\right)$$ where f(∙) is the experimentally measured parabolic correspondence between V_G1,on and V_G2 (Fig. 2g), N denotes the iteration index, V_base represents the minimum V_G1,on, and α denotes the scaling constant. Based on this equation, the iterative determination of V_G1,on results in V_G1,on either converging or diverging, depending on the value of α (more detailed in the Supplementary Note 1).

Figure 3a−j depict the output values of V_G1,on over 100 iterations for various values of α, starting with an initial V_G2 of 0.2 V. When α is set to 4, V_G1,on converges to the vertex of the parabola as shown in Fig. 3a, which results in a single, constant output value as represented Fig. 3f. Furthermore, increasing α to 6.3 causes V_G1,on to oscillate between two points on a parabola (Fig. 3b), which generates two alternating output values (Fig. 3g). Further increasing α to 8 leads to oscillations between four distinct points (Fig. 3c), thereby generating four periodic output values (Fig. 3h). The V_G1,on no longer stabilizes to fixed points with an α of 9.5. Instead, it exhibits chaotic fluctuations (Fig. 3d) that lead to random number generation (Fig. 3i). Interestingly, when α is slightly increased to 9.7, V_G1,on resumes oscillating between three points (Fig. 3e), periodically producing three repeating output values (Fig. 3j). Note that throughout all values of α, the parabolic relationship between V_G1,on and V_G2 inherently confines the range of the iterative V_G2 values within 0 to 2.2 V.

Fig. 3 Behavior of V_G1,on with the change in α value. [Images not available. See PDF.]

Parabolic relationship between V_G1,on and V_G2, and oscillation points for α of 4 (a), 6.3 (b), 8 (c), 9.5 (d), and 9.7 (e). Iterative behavior of V_G1,on for α of 4 (f), 6.3 (g), 8 (h), 9.5 (i), and 9.7 (j). k Output values of V_G1,on from the final 30 iterations, as α increases by 0.1, ranging from 4 to 10.

Figure 3k consolidates the V_G1,on values from the final 30 iterations after performing 100 iterations for α values ranging from 4 to 10, with increments of 0.1. This behavior demonstrates a chaotic bifurcation^{34, 35, 36–37}, where as α increases, the number of oscillating V_G1,on values progressively branches out. At specific intervals, the system transitions into chaotic regimes marked by non-repeating and unpredictable V_G1,on values. Eventually, it stabilizes into new periodic states characterized by discrete points.

Under ideal conditions, chaotic behavior is determined by the initial conditions. However, for PFTs, the butterfly effect³⁸ that arises from inherent device variability (detailed in Supplementary Fig. 3) enables the generation of entirely unpredictable random values—even when the initial conditions are known. A comparison between the ideal scenario (excluding device variability) and the actual measurement results is illustrated in Supplementary Fig. 4. To further quantify the transition from periodic to chaotic behavior, we computed the largest Lyapunov exponent (LLE) of the experimental sequences as a function of α, as summarized in Supplementary Fig. 5. The bifurcation diagram in Supplementary Fig. 5a shows the progressive splitting of V_G1,on values, while Supplementary Fig. 5b demonstrates that the LLE changes from negative (periodic regime) to positive (chaotic regime) as α increases. This provides rigorous quantitative evidence that the PFT undergoes a deterministic-to-chaotic transition in agreement with the bifurcation analysis. In addition, as shown in Supplementary Fig. 6, the quantized bit sequence generated from the PFT and post-processed by down-sampling, multi-tap parity XOR, and a von Neumann corrector successfully passed all tests of the NIST SP 800-22 test suite.

The parameter α serves as a pivotal tunable factor, which facilitates controlled transitions between periodic and chaotic behaviors within the system. By selecting suitable α values, the system can be engineered to produce outputs that either oscillate between multiple discrete values or generate entirely random outputs from a single PFT. This tunability imparts significant flexibility and enables the modulation of the randomness characteristics to suit specific application requirements. Moreover, within the chaotic region, the extent of randomness can be finely adjusted by simply varying α (Supplementary Figs. 7 and 8). This feature allows precise control over the amplitude and distribution of the output values. This is particularly advantageous for applications that require tailored random number generation, where the degree of randomness and its controllability are critical for optimizing security and performance parameters.

The iterative feedback mechanism uses the parabolic relationship between V_G1,on and V_G2, governed by the scaling constant α, to enable the controlled generation of periodic and chaotic V_G1,on outputs. Note that the iterative feedback can be directly realized by exploiting the parabolic dependence of I_A on V_G2 at a fixed V_G1, as detailed in Supplementary Note 2. The observed bifurcation and subsequent transition to chaos highlight the potential of this approach for applications requiring versatile and tunable random number generation. This advancement significantly enhances the utility of the PFT in developing secure and efficient data processing systems.

During the random number generation process, the PFT consistently operates with gate voltages below 2.2 V. This low-voltage operation mode preserves the integrity of the gate-insulating layer and ensures that the PFT can reliably generate numerous random numbers. Supplementary Fig. 9 depicts the endurance of a PFT subjected to multiple read pulses. Even after applying up to 10¹⁰ times read operations, the PFT’s V_G1,on and SS exhibit minimal variation (0.1% in V_G1,on, and 0.8% in SS), which confirms that it can reliably generate a nearly infinite number of random numbers. It should be noted that, unlike previously reported CMOS probabilistic bit implementation that also exploits the floating-body effect and positive feedback³⁹, the randomness in our work arises from a mathematical chaotic regime and the inherent variability of the PFTs as the source of the butterfly effect, providing a fundamentally distinct and reproducible entropy source rather than only relying on the inherent stochasticity of individual devices. Supplementary Fig. 10 provides the benchmarking results of the PFT-based random key generation with previously reported works.

Charge-trap flash memory array

For real-world applications, the secure storage of the encrypted information is as critical as the encryption process itself^{40, 41–42}. By integrating the CTF devices with the PFT, a robust hardware-based solution can be achieved. Note that the PFT and CTF share key fabrication steps on the same SOI substrate (See the Method section for the details), enabling seamless co-fabrication in a single process flow. This intrinsic process compatibility allows direct integration of entropy generation (PFT) and secure storage (CTF) without additional complexity. This integration ensures both data integrity and confidentiality, providing a comprehensive approach to secure data storage. Fig. 4a−c depict a schematic of the CTF device, as well as a schematic and optical image of the 25 × 4 AND-type CTF array. Fig. 4d presents the I_D-V_G transfer curves of 50 randomly selected devices from the CTF array, demonstrating the excellent uniformity of device performance across the array. During the measurement of each device in the array, electrical inhibition was achieved by applying 0 V to the non-selected bit-lines (BLs) and − 1 V to the non-selected word-lines (WLs), while 0 V was applied to every source-line (SL). Furthermore, the charge-trap capability of the ONO layer enables the CTF device to perform a non-volatile memory function as shown in Fig. 4e. The program operation was carried out by applying a pulse of 10 V (base voltage = 0 V) with a duration of 100 μs for 100 repetitions, while the erase operation was performed by applying a pulse of 0 V (base voltage = 10 V) with a duration of 1 ms, for 100 times. Through the program and erase operations, the CTF device achieved a memory window of approximately 2 V.

Fig. 4 Charge-trap flash (CTF) memory array and electrical characteristics. [Images not available. See PDF.]

a Schematic 3-D image of the CTF device. b Schematic and (c) optical image of the fabricated 25 × 4 AND-type CTF array. dI_D-V_G transfer curves of 50 devices in the CTF array. eI_D-V_G transfer curves of the CTF device in the pristine, programmed (10 V/100 μs/100 times), and erased (10 V/1 ms/100 times) states. f Randomly selected 25 devices in the CTF array exhibiting a 4-bit state.

In order to enable the storage of encrypted 4-bit fingerprint images, it is essential to ensure that each device within the CTF array has 16 distinct memory states. To validate this capability, fine-tuning (for details, see Supplementary Fig. 11) was performed on 25 randomly selected devices within the CTF array. These devices were programmed to achieve 16 discrete conductance levels. In addition, an inhibition scheme was utilized to prevent interference with adjacent cells during the programming and erasing of individual devices within the array, which ensures precise and isolated operation (Supplementary Fig. 12). During programming, a 10 V pulse was applied to the selected WL, while the selected BL/SL were grounded, and the unselected BLs/SLs received half of that amplitude (5 V), with all unselected WLs grounded. For the erase operation, to avoid using negative voltages, we adopted a biasing scheme in which a 10 V bias was applied to the selected BL and SL while a 10 V/0 V/10 V pulse was applied to the selected WL. The unselected BLs/SLs were biased at 5 V, and all unselected WLs were biased at 10 V. As a result, all 25 devices exhibit 16 conductance levels within a uniform range, as demonstrated in Fig. 4f. Supplementary Fig. 13 shows the reliability of CTF devices in terms of endurance and retention characteristics.

Fingerprint-image encryption using PFT

By setting α within the region where the PFT exhibits chaotic behavior, a random sequence of V_G1,on values can be generated. In this study, we validated the successful encryption and decryption of 4-bit fingerprint images (83 × 76 pixels)⁴³, which are commonly used for bio-authentication. By leveraging the random sequences generated through the PFT as encryption keys, fingerprint images can be encrypted through an XOR operation. Since the V_G1,on values from the PFT are analog random values, each value was quantized to four bits before performing an XOR operation with each pixel of the fingerprint image to implement the encryption. Due to the reversible nature of the XOR operation (wherein applying the XOR operation twice restores the original value), the encrypted image can be decrypted by performing an XOR operation with the same key used for encryption. Figure 5a displays the 6,308 V_G1,on values generated for each pixel of the fingerprint image using an α value of 9.5. These V_G1,on values were quantized into 16 discrete levels, as illustrated in Fig. 5b. To assess the security of the quantized V_G1,on sequence against external machine learning (ML) attacks, we trained a long short-term memory (LSTM)-based model on the first 10,000 bits and attempted to predict the remaining bits. As shown in Supplementary Fig. 14, the sequence generated by the PFT is robust against ML attacks, with no clear predictability beyond random chance.

Fig. 5 Fingerprint image encryption using PFT. [Images not available. See PDF.]

a Random V_G1,on values with α of 9.5. b Random V_G1,on values after 4-bit quantization. c Original and (d) encrypted fingerprint images. Pixel-intensity histograms for the (e) original and (f) encrypted fingerprint images. g Original and (h) encrypted fingerprint images in the frequency domain after the Fourier transform. i Intensities of 25 pixels from the encrypted image and their corresponding device conductance within the CTF array.

Figure 5c shows an example of the original fingerprint image. Figure 5d presents the encrypted image, which was obtained by performing a pixel-wise XOR operation between the original fingerprint image and the quantized encryption key. Fig. 5e, f display the pixel intensity histograms for the original and encrypted images, respectively. It should be noted that the XOR operation was not implemented by on-chip logic in this work. Instead, the random outputs experimentally obtained from the PFT were quantized into 4-bit sequences, and the XOR operation was applied externally in software. These histograms demonstrate that the encrypted image has completely obscured the information of the original image. Furthermore, to validate the effectiveness of the encryption, we performed Fourier transforms on the images to analyze their features in the frequency domain. Figure 5g, h show the Fourier-transformed original and encrypted images, respectively. While the original image displays distinct patterns in the frequency domain, the encrypted image lacks any discernible patterns, which further confirms the successful implementation of encryption.

In addition, to verify that encrypted images can be accurately stored in the CTF array on the same substrate using PFTs, we mapped the intensity of 25 pixels from the encrypted image to the CTF array. As shown in Fig. 5i, the 4-bit pixel values are successfully mapped to the conductance of each device within the CTF array. This demonstrates that by integrating PFTs and the CTF array on a single substrate, it is possible to realize efficient and highly secure encryption and storage devices.

Discussion

In this work, we report, for the first time, the turn-on phenomenon driven by band-to-band tunneling (BTBT) in positive feedback transistors (PFTs). We further demonstrated a novel application of this phenomenon as a stable random key generator for secure data encryption. The BTBT mechanism in the PFT, occurring under high V_G2 (voltage applied to G2 of PFT), was thoroughly investigated, revealing a parabolic relationship between V_G2 and V_G1,on (the turn-on voltage of the PFT). Using this parabolic relationship, we experimentally observed chaotic bifurcation through the iterative feedback of V_G1,on and V_G2, where the behavior of the output V_G1,on varies with different values of α. Our analysis confirms that for specific α values, various repetitive patterns of V_G1,on emerge, while for certain intervals, completely random outputs were generated.

By utilizing this random output, we successfully encrypted and decrypted a fingerprint image using the XOR operation. The encrypted image showed complete randomness, effectively obscuring the original data, while decryption restored the original image perfectly. This validated the effectiveness of our new approach. Furthermore, we demonstrated that the charge-trap flash memory (CTF) array is capable of securely storing encrypted information. This integration enables the simultaneous implementation of data encryption (via the PFT) and secure data storage (through the CTF array) within a single wafer. In this way, a cohesive and scalable solution for integrated encryption and memory functionality can be provided. This study not only highlights the potential of PFTs as random key generators but also offers new insights into the device’s behavior under chaotic conditions. These findings pave the way for a secure and flexible approach to data encryption based on physical randomness.

Methods

Fabrication process of PFTs

The fabrication was performed on six-inch silicon-on-insulator (SOI) wafers to ensure effective device isolation and to form the floating body utilized in the PFT (see Supplementary Fig. 1a). The active regions for each device were defined using photolithography, followed by oxidation and ion implantation to create the p and n-doped areas (refer to Supplementary Fig. 1b). Then, n⁺-doped polycrystalline silicon (poly-Si) was deposited and patterned to form the gates of the nMOS, pMOS, and gate 1 of the PFT (Supplementary Fig. 1c). After ion implantation for the n-doped body of the PFT, a SiO₂/Si₃N₄/SiO₂ (ONO) layer was deposited to serve as the charge-trap layer for the CTF device and to isolate the two gates of the PFT. Subsequently, n⁺-doped poly-Si was deposited and patterned to form the gate of the CTF device and gate 2 of the PFT (Supplementary Fig. 1d). Finally, an ion implantation and activation process was performed to create the source/drain regions of the nMOS, pMOS, and CTF, as well as the cathode/anode of the PFT (Supplementary Fig. 1e). These fabrication steps enable the seamless integration and co-fabrication of the nMOS, pMOS, CTF and PFT on a single wafer.

Measurement setup

A probe station, semiconductor parameter analyzers (B1500A and 4156 C), and a switching matrix were utilized for the measurement of the PFTs and the CTF array. Chaotic bifurcation of the PFT was experimentally carried out by reapplying V_G2 corresponding to V_G1,on, using the EasyEXPERT software within the B1500A. The CTF array was measured using a switching matrix connected to the 4165 C. Program and erase pulses were applied through a pulse generator unit. During the read operation of the CTF array, the selected WL was biased at the read voltage, while all unselected WLs were held at − 1 V as an inhibition bias. As confirmed in Fig. 4e, cells under − 1 V gate bias remain off in both the programmed and erased states, which effectively suppresses cross-talk from unselected cells.

Fingerprint image dataset

To demonstrate the image encryption using the PFTs, we used the Sokoto Coventry Fingerprint Dataset (SOCOFing), which is a biometric fingerprint dataset designed for academic research purposes. We cropped the fingerprint image to dimensions of 83 × 76 pixels to remove unnecessary background regions.

Acknowledgements

This work was supported by the BK21 FOUR Program, Seoul National University in 2025, and the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (RS-2025-10032968 and RS-2024-00405200).

Author contributions

J.I. (Jiseong Im) conceived, designed, and performed the experiments and wrote the manuscript. J.I. (Jiseong Im), J.K. (Jonghyun Ko), and S.Y.W. designed and fabricated the devices. J.I. (Jisung Im) performed the device simulation. J.H., R.-H.Koo., S.-H.Park analyzed the data and revised the manuscript. J.K. (Jangsaeng Kim) and W.S. participated in the result discussion and revised the manuscript. S.Y.W. and J.-H.L. proposed and supervised this work.

Peer review

Peer review information

Nature Communications thanks Cai-Hua Wan, Yimin Wu and the other anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Data availability

All the relevant data are available from the authors.

Code availability

All the relevant codes used for the simulation are available within the article and its Supplementary Information or from the corresponding authors upon request.

Competing interests

The authors declare no competing financial or non-financial interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-025-66398-0.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

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