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As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by intensive computational tasks, parallel execution of tasks, thermal coupling effects, and limitations on cooling methods. High temperatures may further decrease the performance of the chip and the overall system. In this paper, we have studied different parameters related to core performance. The MSI Afterburner utility is used to extract the hardware parameters. Single and multivariate analyses are carried out on core temperature, core usage, and core clock to study the performance of all cores. Single-variate analysis shows the need for action when core temperatures, core usage, and clock speeds exceed threshold values. Multivariate analysis reveals correlations between these parameters, guiding optimization strategies. We have also implemented the ARIMA model for core temperature estimation and obtained an average RMSE of 2.44 °C. Our analysis and ARIMA model for temperature estimation are useful in developing smart scheduling algorithms that optimize thermal management and energy efficiency.
Details
Afterburners;
Trends;
Microprocessors;
Optimization;
Thermal coupling;
Performance evaluation;
Workloads;
Energy consumption;
High temperature;
High performance computing;
Processing speed;
Scheduling;
Machine learning;
Embedded systems;
Virtual reality;
Temperature;
Energy management;
Multivariate analysis;
Energy efficiency;
Processors;
Literature reviews;
Algorithms;
Thermal management;
Artificial intelligence;
Parameters
; Srinivasa, Rao Y 2
1 Department of Information Technology, SIES Graduate School of Technology, University of Mumbai, Navi Mumbai 400706, India, Department of Computer Engineering, Sardar Patel Institute of Technology, University of Mumbai, Mumbai 400058, India
2 Department of Electronics & Telecommunication Engineering, Sardar Patel Institute of Technology, University of Mumbai, Mumbai 400058, India; [email protected]