Fully integrated hybrid multimode-multiwavelength photonic processor with picosecond latency

Abstract

High-speed signal processing is crucial for increasing the data throughput in next-generation communication systems, including multiple-input multiple-output (MIMO) networks, emerging 6G architectures, and beyond. However, system scaling inevitably increases hardware complexity, computational demands, and the challenges associated with digital signal processing (DSP). The physical limitations of electronic processors constrain computational throughput and increase DSP latency, creating a critical bottleneck. Photonic processors offer a compelling alternative, with inherent advantages of broad bandwidth, low loss, massive parallelism, and ultralow latency. Nevertheless, their scalability has been hindered by integration challenges, large device footprints, and on-chip multiplexing limits. Here, we present a scalable, monolithically integrated hybrid photonic processor that simultaneously leverages mode-division and wavelength-division multiplexing. The processor integrates adiabatic mode multiplexers, mode-selective microring resonators, and balanced multimode photodetectors on a single chip. We experimentally demonstrate real-time optical MIMO signal unscrambling at 5 Gb/s and radio frequency signal unjamming in phase-shift keying transmission, performed entirely in the analog optical domain with a processing latency of just 30 ps. This work opens a pathway toward energy-efficient, ultralow-latency processors for future wireless and optical communication networks.

Researchers present a scalable hybrid photonic processor that uses mode- and wavelength-division multiplexing to overcome electronic limits, demonstrating ultralow latency and real-time signal processing for next-generation communication networks.

Introduction

Multiple-input multiple-output (MIMO) links are fundamental to today’s high-performance communication infrastructure, supporting increased data rates and enhanced spectral efficiency in both wireless and optical networks^1,2. To process high-speed MIMO signals, analog radio-frequency (RF) or optical signals are often converted into digital signals and processed by electronic digital signal processors (DSP)^3,4. However, as communication standards evolve toward massive MIMO configurations, DSP throughput and latency have emerged as critical bottlenecks, impeding real-time data processing^5,6. These challenges extend to RF signal processing applications, such as interference cancellation⁷. Electronic processors increasingly struggle to meet the demands of such high-throughput tasks due to inherent limitations including bus latency, power leakage, and signal distortion^8,9. Recent advances in photonic processors offer promising alternatives, particularly in compute density (defined as the number of multiply-accumulate (MAC) operations per second per unit area) and energy efficiency (energy consumed per MAC)^10,11. Photonic processors offer inherent advantages such as low propagation loss, high bandwidth, and resilience to large fan-in/fan-out configurations^{12, 13, 14–15}. Moreover, photonic interconnects are immune to parasitic resistance and capacitance effects¹⁶. Consequently, photonic MAC processors have the potential to achieve attojoule per MAC energy efficiency, picosecond-scale latency, and compute densities exceeding petaMAC per second per mm², outperforming conventional digital processors^12,17,18.

Various photonic platforms have been explored, including those based on discrete components, free-space optics, and integrated photonics^{19, 20–21}. Among these, on-chip photonic processors fabricated using CMOS-compatible processes offer high-density integration, low-latency operation, and energy-efficient, real-time signal processing²². These processors exploit multiple degrees of freedom inherent to light, enabling parallel and distributed processing through time-division multiplexing (TDM), space-division multiplexing (SDM), and wavelength-division multiplexing (WDM). TDM-based photonic processors, for example implemented using high-speed thin-film lithium niobate modulators, offer fast operation but require ultrafast modulation and detection electronics, which introduces synchronization complexity and increases power consumption²³. SDM-based architectures, typically implemented with Mach-Zehnder interferometer (MZI) meshes²⁰, provide spatial parallelism but rely on coherent interference, making them highly sensitive to phase fluctuations. Furthermore, MZI-based designs are bulky and require extensive control parameters, limiting scalability. In contrast, WDM-based processors, which utilize microring resonators (MRRs) or crossbar arrays, offer incoherent, phase-insensitive operation with compact footprints^12,24. However, their scalability is constrained by the finite free spectral range (FSR) of MRRs, which limits the number of usable wavelength channels to fewer than 148^11,25. Despite the diversity of multiplexing strategies, on-chip photonic processors continue to face scalability challenges, especially for large-scale applications such as massive MIMO signal processing.

Recent interest in hybrid multiplexing approaches provides a promising path to enhancing both scalability and throughput. Here, throughput refers to the number of operations performed per second, where each MAC operation comprises a multiplication and an addition. Combining WDM with mode-division multiplexing (MDM) enables scaling of WDM-based processors beyond the MRRs FSR-imposed limit, while preserving the advantages of WDM. MDM further boosts processing capacity by exploiting orthogonal spatial modes within a single waveguide. In a hybrid MDM-WDM architecture, n WDM wavelength channels can be reused across m MDM spatial modes, effectively scaling capacity to m × n. However, practical implementation of multimode systems poses significant challenges. Variability in mode confinement, mode coupling, and eigenmode propagation across different devices can lead to intermodal crosstalk, loss, and increased design complexity, particularly in mode switching and routing²⁶. While previous works have explored hybrid MDM-WDM in fiber-based photonic beamformers²⁷, these systems remain off-chip and lack monolithic integration. On-chip MDM photonic processors based on single-mode all-pass MRRs and MZIs have also been proposed^28,29, but they offer limited functionalities and multimode compatibility. Specifically, they do not support negative weighting or direct multimode addition; instead, mode signals must be demultiplexed and individually detected before summing the photocurrents, defeating the purpose of MDM and complicating single-chip integration. Moreover, MZI-based systems lack WDM compatibility and employ passive multimode combiners, whose outputs are highly dependent on phase and amplitude of input signals, necessitating additional phase-shifting and calibration circuitry.

In this work, we present a monolithically integrated, fully functional MDM-WDM-compatible processor. This processor addresses the WDM scalability limits imposed by the FSR of MRRs³⁰. The processor architecture (Fig. 1) comprises an adiabatic mode multiplexer (MUX), a mode-selective MRR array, and multimode balanced photodetectors (PDs). Inputs are encoded onto different combinations of wavelength and mode channels, allowing wavelengths to be reused across spatial modes. The MDM-WDM weight banks are made mode-selective by tuning the bus waveguide width and wavelength-selective by adjusting the ring radius. The weighted signals are then summed optically at the balanced multimode PD. Our design overcomes the limitations of previous works by fully integrating mode-selective, WDM-compatible MRR weight banks with multimode germanium PDs in a balanced configuration on a single-chip. This allows direct mode weighting and addition of signals across both wavelength and modes domains while supporting positive and negative weights. The adiabatic mode multiplexer further relaxes fabrication tolerances by eliminating stringent requirements on selective mode coupling. We experimentally demonstrate two proof-of-concept MAC processors: one with 2 modes and 2 wavelengths, and another with 4 modes and 1 wavelength. While the total number of channels is limited to 4, these demonstrations validate the scalability of MDM-WDM approach and highlight its potential for future large-scale, high-speed, and real-time signal processing.

Fig. 1 Schematic of the large-scale fully integrated hybrid multimode-multiwavelength photonic processor. [Images not available. See PDF.]

a The photonic processor is comprised of a mode multiplexer, tunable mode-selective microring resonators, and multimode balanced photodetectors. Inputs x_ij are encoded in both the mode domain i and the wavelength domain j, represented by different colors and field profiles. b The mode multiplexer combines single-mode signals into different modes to be input to the processor. c The mode-selective microring resonator (MRR) is mode-selective and wavelength-selective by adjusting the bus waveguide width and ring radius, respectively, imprinting the weight matrix elements w_ij on the input signal. The controller drives the MRR heater to tune its resonance wavelength. d The integrated multimode photodetectors combine the weighted output signals from the mode-selective MRR weight bank. The photonic processor is capable of performing a wide range of applications, directly in the mode domain, suitable for applications such as signal unscrambling, signal unjamming, and tensor core processing.

As the channel capacity of transmission links approaches the nonlinear Shannon limit, the demand for increased capacity necessitates a paradigm shift. MDM, particularly in multimode fiber (MMF) combined with MIMO techniques, holds great promise. However, traditional MIMO systems often experience mode scrambling caused by modal dispersion, scattering, mode mixing, diffraction loss, and crosstalk–all of which significantly complicate signal reconstruction at the receiver^{31, 32–33}. Our fully integrated MDM-WDM-compatible photonic processor overcomes these challenges by enabling direct, arbitrary access to individual modes and wavelengths, supporting reconfigurable, real-time unscrambling of mixed-mode signals in massive MIMO links. As a proof of concept, we demonstrate real-time unscrambling of two spatial modes at a bit rate of 5 Gb/s with an optical processing latency of just 30 ps. We also demonstrate a scalable RF signal unjamming application using the same architecture, with a processing bandwidth of 2.5 GHz. To our knowledge, this is the first monolithic, fully integrated MDM-WDM photonic processor capable of direct negative and positive mode weighting and mode addition via integrated multimode balanced photodetectors. Furthermore, the processor achieves approximately 4.1 times higher throughput compared to traditional WDM processors where outputs of multiple processor instances are electrically connected. This work establishes a compelling foundation for the next generation of scalable, energy-efficient, and high-speed photonic processors for advanced signal processing tasks.

Results

Multimode photonic processor

Figure 1 illustrates the architecture of the MDM-WDM-compatible on-chip photonic processor. The system comprises three key components: an adiabatic mode multiplexer, mode-selective MRRs, and balanced multimode photodetectors. A microscope image of the fabricated processor, along with the measured performance of each component, is shown in Fig. 2. To realize hybrid multiplxing, all photonic devices must simultaneously support both multimode and multiwavelength operation. Accordingly, each component is engineered to optimize modal loss, crosstalk, and responsivity. The adiabatic directional coupler, used as the mode multiplexer, features a gradually varying waveguide width to support robust mode operation. The index-matching point lies at the midpoint of the coupler (see Supplementary Section S1). This design offers two principal advantages: (1) it guarantees an index-matched coupling point that compensates for fabrication variations³⁴, and (2) it suppresses back-coupling of higher-order modes into the fundamental mode at the input. Since the coupler relies on index matching to convert the input single mode into a higher-order mode, all other modes in the multimode waveguide pass through unaffected. The full multiplexer/demultiplexer (MUX/deMUX) stage is realized by cascading adiabatic couplers. Figure 2a shows the mode MUX/deMUX layout. We characterized the insertion loss and crosstalk by launching light into each input port and measuring transmission spectra at each output port of back-to-back connected identical multiplexers. As shown in Fig. 2b, the MUX/deMUX exhibits broadband operation over a 40 nm range, with measured insertion losses of 1.9 dB, 1.5 dB, 1.5 dB, 3 dB and maximum crosstalk of 33 dB, 28 dB, 28 dB, 26 dB for TE₀, TE₁, TE₂ and TE₃ modes, respectively. The design parameters are summarized in Table S1 in the Supplementary information. As a proof of concept, we implemented a four-mode MUX/deMUX. While our demonstration is limited to four modes, similar devices supporting up to 10 modes with comparable performance have been reported³⁵. Increasing the number of supported modes typically requires wider waveguides and more complex mode multiplexers, which increases chip area. However, this overhead can be mitigated by using inverse-designed photonic components³⁶, which have been shown to significantly reduce the footprint of mode multiplexers³⁷.

Fig. 2 MDM-WDM-compatible photonic processor. [Images not available. See PDF.]

a Image of the four-mode multiplexer. b Transmission spectra of the multiplexer measured from back-to-back connected identical multiplexers for TE₀, TE₁, TE₂, and TE₃ input modes. c Image of the photonic processor fabricated on a standard silicon photonic platform. d Zoomed image of the mode-selective microring resonator. e The through (blue line) and drop (orange line) transmission spectra for TE₀ and TE₁ modes in the 2-mode and 2-wavelength processor. f The through (blue line) and drop (orange line) transmission spectra for TE₀, TE₁, TE₂, and TE₃ modes in the 4-mode and 1-wavelength processor. g Zoomed image of the designed multimode photodetector. h Photodetector responsivity for TE₀, TE₁, TE₂, and TE₃ mode channels at a reverse bias voltage of 3V. i Measured normalized frequency response of the photodiode for TE₀, TE₁, TE₂, and TE₃ modes. The 3-db optoelectronic bandwidth reaches  ~17 GHz. j Recorded eye diagrams from the photodetector for different modes at an operating speed of 10 Gb/s.

The weight bank in the processor consists of an array of MRRs, each designed for both mode and wavelength selectivity (Fig. 2d). Unlike conventional single-mode MRRs, each ring is uniquely defined by a specific bus waveguide width (for mode selectivity) and ring radius (for wavelength selectivity)³⁸. Using mode index dispersion curves, the rings are carefully engineered to strongly couple only the desired mode. This architecture allows all n WDM channels to be reused across m spatial modes, effectively scaling the WDM weight bank capacity by a factor of m. The practical scalability limit is determined by factors such as chip area, MRR insertion loss, and the number of required MRR drivers. Excessive insertion loss can lower the optical signal power at the photodetector to near the noise floor, reducing accuracy. While scaling to n × m MRRs may increase optical losses and control complexity, these limitations can be mitigated through the co-integration of driver electronics and the use of higher optical input power. Each MRR has a thermal tuner that adjusts its resonance frequency to set the desired weight. While thermal tuning consumes power (typically in the milliwatt range), it could be more energy-efficient than DSP approaches, depending on the scale of the system^39,40. These advantages stem from the inherently low resistive and capacitive effects in photonic circuits, enabling high bandwidth and energy efficiency independent of signal frequency, unlike in DSP systems. Moreover, energy efficiency can be further improved by adopting alternative non-volatile tuning mechanisms, such as phase change materials¹⁷ or photochromic materials⁴¹, but require post-fabrication processing. Further details on the ring design are provided in Supplementary Section S2.

Measured through and drop port responses for two weight bank configurations—2-mode/2-wavelength and 4-mode/1-wavelength—are shown in Fig. 2e, f, respectively. The results confirm that each ring couples selectively to the correct mode and wavelength. However, we observe finite modal crosstalk between the TE₂ and TE₃ modes. In particular, the drop spectra of TE₂ and TE₃ show minor peaks aligned with each other’s main resonances. Additionally, the extinction ratios for these two modes are reduced, which we attribute to an overestimation of the coupling coefficient between the bus waveguide and the ring. While the weights remain functional, future designs can improve extinction by increasing the coupling strength.

To realize the photonic processor, we integrated a balanced multimode PIN germanium-on-silicon vertical photodetectors (BPD) at the output of the through and drop multimode waveguides (Fig. 2g). For efficient multimode operation, the BPD are designed (see Supplementary Section S3) with two off-centered metal contacts on the N-doped region, reducing attenuation near modal power peaks and improving responsivity across modes⁴². Each detector has an active area of 10.6 μm × 27.2 μm, with measured responsivities ranging from 0.83 to 1.05 A/W for TE₀ through TE₃ modes (Fig. 2h). The bandwidth of the multimode photodetector is consistent across modes, measured between 16 and 17 GHz (Fig. 2i). The measured eye diagrams (Fig. 2j) validate high-speed operation of the PD across all modes. More generally, optimized PIN germanium-on-silicon vertical photodetectors can achieve  >50 GHz bandwidths through dimension optimization and inductive peaking^42,43. In summary, we demonstrate a fully integrated MDM-WDM-compatible on-chip photonic processor with two configurations: 2-mode/2-wavelength and 4-mode/1-wavelength (Fig. 2c). The processor incorporates mode multiplexers, mode-selective microring weight banks, and balanced multimode photodetectors, providing a reconfigurable, high-speed platform for real-time signal processing across a broad range of applications.

Optical signal unscrambling

In optical MIMO links that utilize multiple spatial modes, effects such as fiber bending, modal dispersion and scattering induce mode scrambling, which distorts transmitted signals and significantly increases the bit error rate (BER). The BER is further influenced by factors including input power, intersymbol interference, and mode-dependent loss⁴⁴. These degradations are particularly pronounced at higher baud rates, resulting in elevated BER and reduced transmission capacity. Conventional MIMO-based communication systems rely on complex DSP to recover the original signals, leading to increased latency, power consumption, and hardware complexity^{45, 46, 47–48}. In contrast, our photonic processor enables real-time unscrambling of high-speed MIMO signals entirely in the analog optical domain. Unlike prior photonic systems, which typically require demultiplexing of signals into separate detectors followed by summation of their output currents²⁸, our processor features integrated multimode photodetectors that allow direct on-chip processing of scrambled multimode signals. Additionally, our processor accepts inputs natively in the mode domain, eliminating the need to convert all multimode signals to the fundamental mode prior to processing. Together, the use of mode-domain inputs and integrated multimode PDs allows for full system integration and eliminates the need for complex external signal handling.

As a proof of concept, we experimentally demonstrate real-time unscrambling of two modes, TE₀ and TE₁, at data rates of 5 Gb/s. Using an arbitrary waveform generator (AWG), we emulated the scrambling that occurs in multimode fiber transmission in a controlled fashion by applying predefined scrambled modulation to the original signals. The scrambling of MIMO signals can be modeled by a scrambling matrix A. We scrambled two raised cosine non-return-to-zero (NRZ) pseudorandom binary sequence (PRBS) signals of length 2¹³-1. The signals were modulated onto TE₀ and TE₁ spatial modes at the same wavelength using Mach-Zehnder modulators (MZMs).

The scrambled signals are then input to the 2-mode, 2-wavelength photonic processor for real-time unscrambling. Signal recovery is achieved using pilot signals, known sequences transmitted alongside the data, which are used to estimate the scrambling matrix A⁴⁹. The processor performs matrix-vector multiplication (MVM) by applying the inverse of the scrambling matrix A⁻¹ through the mode-selective MRR weight bank, followed by signal summation at the multimode PDs. Details of the scrambling matrix estimation and experimental setup are provided in the Methods Section and Supplementary Section S4. Unlike conventional DSP approaches, our system processes signals directly in the analog optical domain, enabling high parallelism, low latency, wide bandwidth, and low energy consumption within a compact footprint. Furthermore, this MDM-WDM architecture operates incoherently, eliminating the need for phase tuning and avoiding phase instability and interference issues common in coherent MVM systems.

Figure 3 shows eye diagrams of the original, scrambled, and recovered signals. The scrambled signals at 5 Gb/s exhibit closed eyes, corresponding to a theoretical BER of 50%. After applying the inverse scrambling matrix using the thermally-tuned MRR weights, the recovered signals exhibit clear eye-opening (Fig. 3a), with measured BERs of 2.6 × 10⁻⁵ and 5.7 × 10⁻⁶ for the TE₀ and TE₁ channels, respectively, at an input power value of −6 dBm. Figure 3b shows the estimated BER as a function of input power for both modes. The TE₀ and TE₁ modes exhibit power penalties of approximately 6 dB and 4 dB, respectively, at the input power value of −6 dBm. These penalties are primarily attributed to modal crosstalk and limited bit precision in the microring weight settings. Performance can be further improved by optimizing device design and fabrication. Once the weights are configured, the processor operates entirely in the optical domain, with an estimated optical processing latency of 30 ps—the time it takes for the optical signal to propagate through and be processed by the circuit. This low latency makes our processor well-suited for high-speed real-time communication and signal processing applications.

Fig. 3 Experimental demonstration of unscrambling optical data streams: Two emulated scrambled signals are encoded on two mode channels (TE₀ and TE₁) and sent to the photonic processor at an operating speed of 5 Gb/s. [Images not available. See PDF.]

a Recorded eye diagrams of the original non-return-to-zero (NRZ) streams ( ${\mathbf{s}}_{{\mathrm{TE}}_0}$ and ${\mathbf{s}}_{{\mathrm{TE}}_1}$ ), the scrambled NRZ streams ( ${\mathbf{x}}_{{\mathrm{TE}}_0}$ and ${\mathbf{x}}_{{\mathrm{TE}}_1}$ ), and the unscrambled NRZ streams ( ${\widehat{\mathbf{s}}}_{{\mathrm{TE}}_0}$ and ${\widehat{\mathbf{s}}}_{{\mathrm{TE}}_1}$ ) using the photonic processor. The first row shows the unscrambling of the TE₀ mode, and the second row shows the unscrambling of the TE₁ mode. b Estimated bit error rate (BER) versus input power for the recovered TE₀ and TE₁ streams compared to the original signals. The photodetectors are reverse biased at 3V using a bias tee, and the signal outputs are recorded using a high-speed scope.

RF signal unjamming

To demonstrate the versatility of our system, we performed RF signal unjamming using blind source separation (BSS). Noisy RF interference is a major challenge in modern communication systems, particularly with the expansion of telecommunications as emerging wireless telecommunication signals are squeezed into limited frequency bands, leading to spectral congestion⁴⁰. MIMO wireless links are especially vulnerable to interference, such as that caused by coexistence conflicts between radar altimeters and 5G cellular networks operating in overlapping frequency bands⁷. While digital post-processing methods have shown effectiveness for interference cancellation in low-speed, narrowband applications, they face serious limitations at gigahertz operating frequencies, including increased latency, reduced energy efficiency, and scalability issues. Moreover, conventional interference mitigation techniques often require prior knowledge of the signal format and data rate—an increasingly impractical assumption as communication systems evolve toward higher carrier frequencies, broader bandwidths, and more diverse modulation schemes. In contrast, our fully integrated photonic processor—featuring a mode-selective microring weight bank and integrated multimode photodetectors—enables on-chip, scalable, and low-latency BSS with wideband processing capabilities. This architecture provides a promising path forward for high-performance wireless technologies. Critically, BSS does not require knowledge of the modulation format or communication standard. It operates under the assumption that source signals are statistically independent and non-Gaussian, making it inherently modulation-agnostic and broadly applicable to a wide range of wireless communication environments¹⁸.

The block diagram for the RF signal unjamming experiment is shown in Fig. 4a. We emulate the mixing of a target signal and a jamming signal, analogous to those received from the MIMO antennas, using two channels of an AWG. These signals are fed into two MZMs operating at the same wavelength. The resulting optical signals are encoded onto the TE₀ and TE₁ mode channels of our 2-mode, 2-wavelength photonic processor.

Fig. 4 Experimental demonstration of signal unjamming: Two emulated mixed signals, generated by mixing a phase-shift keying signal with a jammer, are encoded on two mode channels (TE₀ and TE₁) and sent to the photonic processor. [Images not available. See PDF.]

a Schematic of signal unjamming through the photonic processor. s_PSK represents the phase-encoded original binary phase-shift keying (BPSK) or quadrature phase-shift keying (QPSK) signals, s_J represents the jamming signal, and ${\widehat{\mathbf{s}}}_{\mathrm{PSK}}$ represents the recovered signal. Both are emulated using intensity modulators. The signals are mixed via the propagation matrix A. The input signals are fed into TE₀ and TE₁ channels of the multimode processor. In our experiment, the microring resonators (MRRs) of the same processor were sequentially configured to implement each row of A⁻¹; first to retrieve s_PSK, and then to retrieve s_J, though recovering s_J is not critical for this specific application. b The constellation diagrams show the jammed and unjammed BPSK and QPSK signals respectively, along with their Q-factors (QF).

The target signal is a phase-shift keying (PSK) waveform, modulated onto a 2.565 GHz carrier. The jamming signal is a broadband interferer composed of random samples drawn from a continuous uniform distribution. The resulting mixed signals can be modeled as X = AS, where A is the unknown mixing matrix, S is the matrix whose rows represent the original signal s_PSK and the jammer s_J, and X is the matrix whose rows represent the observed mixed signals. By applying the inverse of the mixing matrix, A⁻¹, the original signal can be recovered via S = A⁻¹X. We implemented BSS using our integrated multimode photonic processor as an efficient method to implement the inverse mixing matrix and cancel interference with minimal prior knowledge about the communication link⁵⁰.

To experimentally recover the original PSK signal, we first recorded the received data from each mode channel at the multimode photodetectors. We then performed offline independent component analysis (ICA) using the FastICA algorithm^51,52 in Python to estimate the unknown mixing matrix (see Methods). The inverse of this matrix was subsequently implemented on-chip by thermally tuning the weights of the MRRs. In our experiment, the same processor is used twice; first, with the MRRs programmed to the first row of the inverse matrix A⁻¹ to recover the desired signal s_PSK; and then reprogrammed with the second row to recover the jamming signal s_J. However, in this specific application, recovering s_J is not necessary for system functionality. Figure 4b shows the constellation diagrams of the jammed and unjammed binary PSK (BPSK) and quadrature PSK (QPSK) signals, along with their corresponding measured Q-factors. Following the application of BSS-based unjamming, a marked reduction in constellation noise is observed, with Q-factor improving from 3.7 to 6.0 for BPSK, and from 2.9 to 5.3 for QPSK. It is important to note that the relationship between Q-factor and BER is nonlinear and governed by the complementary error function (erfc). For example, a Q-factor improvement from 2.9 to 5.3 in QPSK corresponds to a BER reduction from approximately 1.87 × 10⁻³ to 5.79 × 10⁻⁸, representing an improvement of nearly five-orders-of-magnitude. Notably, these BER values are achieved without any error correction. With the addition of standard forward error correction (FEC) techniques, the BER can be further reduced to below 10⁻¹⁸⁵³.

The BSS algorithm used here relies on kurtosis analysis, making it suitable for both coherent and incoherent communication systems, regardless of carrier frequency, modulation format, or channel conditions. Our demonstration validates the real-time separation of desired and jamming signals across a broadband spectrum, enhancing efficient data transmission in MIMO RF links. While this work focuses on introducing a scalable photonic processor architecture through hybrid multiplexing, future iterations could incorporate adaptive BSS control. Prior studies have shown that BSS computation and reprogramming can be completed at rates up to 305 Hz using FPGA-based control with integrated monitoring⁴⁰, enabling adaptation on millisecond-timescale. Such reconfiguration speeds are sufficient for real-world applications, including mitigation of 5G interference in radar altimetry and interference cancellation in the crowded 2.4 GHz band. These findings suggest that future integration of FPGA-based control could enable dynamic, real-time adaptation of our photonic processor in rapidly changing wireless environments.

Discussion

Large-scale photonic processors are essential for applications such as massive MIMO systems⁵⁴ and large-scale MVM in neural networks. To scale photonic processors beyond the inherent limits of WDM, one approach is to combine multiple instances of WDM processors using spatial multiplexing scheme (SMS), or MDM as proposed in this work. In the spatial multiplexing scheme (Supplementary Fig. S10a), the outputs of parallel WDM processors are electronically combined by connecting their PDs and summing their output currents. However, this method introduces a scaling tradeoff: the node capacitance at the output increases with the number of PDs, which reduces the overall operation speed. This increased capacitance arises from both the accumulation of individual PD junction capacitances and the added wiring capacitance. The operations per second (OPS) when combining M WDM processors via SMS is described by the following expression:

1

$${\mathrm{OPS}}_{\mathrm{SMS}}=M\left(2N-1\right)F\frac{C_{\mathrm{PD}}}{M{C}_{\mathrm{PD}}+\left(M-1\right)C_{\mathrm{W}}},$$ where N is the number of wavelength channels per processor, C_PD is the junction capacitance of a reference PD⁴², F is its operation frequency, and C_W is the estimated wiring capacitance between two PDs. Parameter values used in this analysis are listed in Supplementary Section S5.

As an alternative, we propose combining WDM processor instances in the optical domain using MDM (Supplementary Fig. S10b). In this approach, additional spatial modes are supported by increasing the waveguide width, and PD is widened accordingly to maintain high responsivity across all modes. Although the wider detector introduces greater junction capacitance, thus slightly reducing bandwidth, the increase in processing throughput due to mode parallelism more than compensates for this reduction. Notably, this method eliminates wiring capacitance entirely. The corresponding OPS for MDM scaling is given by:

2

$${\mathrm{OPS}}_{\mathrm{MDM}}=M\left(2N-1\right)F\frac{C_{\mathrm{PD}}^{\mathrm{SM}}}{C_{\mathrm{PD}}^{\mathrm{MM}}\left(M\right)},$$ where OPS_MDM is the number of operations per second when employing MDM to combine M WDM processors (also representing the number of supported modes), $C_{\mathrm{PD}}^{\mathrm{SM}}$ is the capacitance of a single-mode PD, and $C_{\mathrm{PD}}^{\mathrm{MM}}\left(M\right)$ is the multimode PD capacitance as a function of the number of modes M. The number of supported modes at each waveguide width, and hence PD capacitance, was computed using the Lumerical MODE simulation package⁵⁵. Figure 5 compares the OPS of SMS and MDM approaches as a function of the number of combined WDM processor instances. As shown, SMS-based scaling results in a decrease in OPS due to increasing output capacitance. In the best case scenario, assuming negligible wiring capacitance, OPS remains constant, but this is rarely achievable in practice. In contrast, the MDM-based approach not only maintains OPS with scaling but also increases it, underscoring the clear advantage of MDM for upscaling large-scale photonic processors.

Fig. 5 Comparison of the number of tera operations per second (TOPS) with up-scaling between wavelength-division multiplexing with spatial multiplexing (WDM-SMS) and wavelength-division with mode-division multiplexing (WDM-MDM) architectures. [Images not available. See PDF.]

In the WDM-SMS approach, the processing speed decreases with system scaling due to increased wiring capacitance. Assuming negligible wiring capacitance, TOPS remains constant with up-scaling. However, in the WDM-MDM architecture, processing speed increases with scaling due to the larger number of supported modes, despite the speed reduction caused by increased junction capacitance. The dotted line is a guide to the eye.

Our demonstrations highlight the processor’s broad applicability across a range of real-world scenarios. It enables signal unscrambling in multimode optical fiber communication links and supports interference cancellation in mission-critical applications such as radar altimeter systems, which facilitate signals exchange between aircraft and ground stations. The processor also lends itself to integration with Internet of Things (IoT) platforms⁵⁶. Critically, because BSS does not require prior assumptions about modulation formats or communication protocols, and given our processor’s wide operational bandwidth of up to 17 GHz, it is compatible with widely adopted wireless standards such as Wi-Fi and Bluetooth, as well as proprietary formats used in image transmission and remote-control systems. These features make the processor particularly well suited for deployment in drones, autonomous ground vehicles, and edge computing platforms within IoT networks^{57, 58, 59–60}. A comprehensive comparison with state-of-the-art photonic architectures across key performance metrics is provided in Supplementary Section S6.

In conclusion, we demonstrated a monolithically integrated MDM–WDM-compatible photonic processor comprising adiabatic mode multiplexers, a mode-selective MRR weight bank, and balanced multimode PDs. By integrating MDM and WDM, we have advanced the scalability and throughput potential of photonic processors. The versatility of the architecture was validated through two representative real-time applications: optical MIMO signal unscrambling and RF signal unjamming. The fully integrated system achieves an optical processing latency of 30 ps. Unlike spatial multiplexing schemes, which suffer from reduced throughput due to increased electrical capacitance, MDM enables scaling while enhancing system throughput. These results position our hybrid MDM-WDM processor as a promising platform for large-scale, high-speed, and real-time signal processing applications.

Methods

Pilot signaling

In an optical MIMO transmission system where multiple mode channels are employed, different signals encoded on different modes experience mixing upon propagation as follows:

3

$$\mathbf{X}=\mathbf{A}\mathbf{S},$$ where S is the matrix whose rows represent the original signals, X is the matrix whose rows represent the corresponding mixed signals, and A is the mixing matrix representing the channel. The original signals can be recovered by applying the unmixing matrix, which is the inverse of the mixing matrix, to the mixed signals as follows:

4

$$\mathbf{S}={\mathbf{A}}^{-1}\mathbf{X}=\mathbf{W}\mathbf{X},$$ where W is the unmixing matrix. However, this unmixing matrix is unknown. One effective approach to estimate the unmixing matrix is to use pilot signals, which are known a priori symbols inserted at regular intervals in the transmitted data stream. In this scheme, pilot symbols of length P are inserted every D data symbols, forming a transmission frame of total length L_f = P + D and resulting in an overhead of P/(P + D).

For example, in a two-mode transmission system, two original signals s₁ and s₂ can be recovered from two mixed signals x₁ and x₂ by transmitting four pilot symbols over two sets. In the first set (p₁), pilot symbols ${{\mathbf{s}}_1}^{p_1}$ and ${{\mathbf{s}}_2}^{p_1}$ are transmitted simultaneously on their respective mode channels. In the second set (p₂), pilot symbols ${{\mathbf{s}}_1}^{p_2}$ and ${{\mathbf{s}}_2}^{p_2}$ are transmitted. The corresponding received mixed signals are ${{\mathbf{x}}_1}^{p_1}$ , ${{\mathbf{x}}_2}^{p_1}$ , ${{\mathbf{x}}_1}^{p_2}$ , and ${{\mathbf{x}}_2}^{p_2}$ . By expanding equation (4), we obtain:

5a

$$\left[\begin{array}{c}\hfill {\mathbf{s}}_1\hfill \\ \hfill {\mathbf{s}}_2\hfill \end{array}\right]=\left[\begin{array}{cc}\hfill w_{11}\hfill & \hfill w_{12}\hfill \\ \hfill w_{21}\hfill & \hfill w_{22}\hfill \end{array}\right]\left[\begin{array}{c}\hfill {\mathbf{x}}_1\hfill \\ \hfill {\mathbf{x}}_2\hfill \end{array}\right],$$ then we substitute by the transmitted pilot symbols and the corresponding received symbols:

5b

$${{\mathbf{s}}_1}^{p_1}=w_{11}{{\mathbf{x}}_1}^{p_1}+w_{12}{{\mathbf{x}}_2}^{p_1},$$

5c

$${{\mathbf{s}}_2}^{p_1}=w_{21}{{\mathbf{x}}_1}^{p_1}+w_{22}{{\mathbf{x}}_2}^{p_1},$$

5d

$${{\mathbf{s}}_1}^{p_2}=w_{11}{{\mathbf{x}}_1}^{p_2}+w_{12}{{\mathbf{x}}_2}^{p_2},$$

5e

$${{\mathbf{s}}_2}^{p_2}=w_{21}{{\mathbf{x}}_1}^{p_2}+w_{22}{{\mathbf{x}}_2}^{p_2},$$ where w_ij are the elements of the unmixing matrix W. By solving Eqs. 5b–e simultaneously, all four elements of W can be estimated. Once the unmixing matrix is known, the original signals can be recovered using Eq. (4). In general, for a transmission system with m mixed signals, at least m² distinct pilot symbols are required to estimate the full unmixing matrix.

Blind source separation

BSS is a powerful technique used to unmix any statistically independent mixed signals without prior knowledge about the signals. According to the central limit theorem, the Gaussianity of the mixed signals is always higher than that of the original signals. Therefore, the BSS algorithm searches for the unmixing matrix that maximizes the non-Gaussianity of the unmixed signals. Kurtosis is the metric used to quantify non-Gaussianity, and it is given by:

6

$$\mathrm{K}\left[{\mathbf{s}}_i\right]=\frac{\mathrm{E}\left[{\left({\mathbf{s}}_i-{\mu }_i\right)}^4\right]}{{\sigma }_i^4}-3,$$ where K is the kurtosis of the signal s_i and μ_i and σ_i are its mean and standard deviation, respectively. The kurtosis of a Gaussian distribution is zero. For BSS, it is often desirable to whiten the received signals by uncorrelating them, zeroing their mean, and normalizing their variance. This whitening process ensures that the vectors of the unmixing matrix are orthogonal.

Starting from the received mixed signals x₁ and x₂ resulting from mixing original signals s₁ and s₂:

7

$${\mathbf{X}}_{\mathrm{c}}=\mathbf{X}-\left[\begin{array}{c}\hfill \mathrm{E}\left[{\mathbf{x}}_1\right]\hfill \\ \hfill \mathrm{E}\left[{\mathbf{x}}_2\right]\hfill \end{array}\right],$$ where X is a matrix with rows representing the mixed signals, x₁ and x₂, while X_c is a matrix containing the corresponding mixed signals that have been centered (i.e., with zero mean). The centered signals are then uncorrelated and their variance is normalized as follows:

8

$${\mathbf{X}}_{\mathrm{w}}=\mathbf{V}{\mathbf{D}}^{\frac{-1}{2}}{\mathbf{V}}^{\mathrm{T}}{\mathbf{X}}_{\mathrm{c}},$$ where X_w denotes the matrix whose rows represent the whitened mixed signals, D is the diagonal matrix containing the eigenvalues of the covariance matrix of the centered signals, and V is the matrix of eigenvectors of the covariance matrix of the centered signals. Since the original signals s₁ and s₂ are uncorrelated, we can deduce that the vectors of the unmixing matrix are orthogonal:

9

$$\mathrm{Cov}\left[{\mathbf{s}}_1{{\mathbf{s}}_2}^{\mathrm{T}}\right]=\mathrm{E}\left[{\mathbf{s}}_1{{\mathbf{s}}_2}^{\mathrm{T}}\right]=0=\mathrm{E}\left[\left({\mathbf{w}}_1{\mathbf{X}}_{\mathrm{w}}\right)\left({{\mathbf{X}}_{\mathrm{w}}}^{\mathrm{T}}{{\mathrm{w}}_2}^{\mathrm{T}}\right)\right]={\mathbf{w}}_1\mathrm{E}\left[{\mathbf{X}}_{\mathrm{w}}{{\mathbf{X}}_{\mathrm{w}}}^{\mathrm{T}}\right]{{\mathbf{w}}_2}^{\mathrm{T}}={\mathbf{w}}_1{{\mathbf{w}}_2}^{\mathrm{T}},$$ where w₁ and w₂ are the rows of the unmixing matrix W that are used to recover s₁ and s₂ from the whitened received signals, respectively. It is noteworthy that we assume the mean of the original signals to be zero, so the recovered signals will have zero mean.

Finally, to recover the original signals, we begin with random vectors w₁ and w₂, then iteratively optimize them using gradient ascent until convergence to a maximum kurtosis as follows:

10a

$$\mathrm{K}\left[{\mathbf{s}}_1\right]=\mathrm{K}\left[{\mathbf{w}}_1{\mathbf{X}}_{\mathrm{w}}\right]=E\left[{\left({\mathbf{w}}_1{\mathbf{X}}_{\mathrm{w}}\right)}^4\right]-3,$$ where w₁X_w is maintained at zero mean and unit variance during optimization. The gradient of this kurtosis is obtained as:

10b

$$\frac{\partial \mathrm{K}}{\partial {\mathbf{w}}_1}=4\mathrm{E}\left[{\left({\mathbf{w}}_1{\mathbf{X}}_{\mathrm{w}}\right)}^3{\mathbf{X}}_{\mathrm{w}}\right],$$ and w₁ update rule is formulated as:

10c

$${{\mathbf{w}}_1}^{j+1}={{\mathbf{w}}_1}^j+4\eta \mathrm{E}\left[{\left({\mathbf{w}}_1{\mathbf{X}}_{\mathrm{w}}\right)}^3{\mathbf{X}}_{\mathrm{w}}\right],$$ where j represents the index of the optimization iteration and η is the learning rate.

Since w₁ and w₂ are orthogonal due to whitening the received signals (Eq. (9)), we can find w₂ using the relation:

11

$${\mathbf{w}}_2={\mathbf{w}}_2-\left({\mathbf{w}}_1{{\mathbf{w}}_2}^{\mathrm{T}}\right){\mathbf{w}}_1.$$ The original signals are then recovered using the optimized weight vectors as follows:

12a

$${\mathbf{s}}_1={\mathbf{w}}_1{\mathbf{X}}_{\mathrm{w}},$$

12b

$${\mathbf{s}}_2={\mathbf{w}}_2{\mathbf{X}}_{\mathrm{w}}.$$

Acknowledgements

We acknowledge the Natural Sciences and Engineering Research, Council of Canada (NSERC), Department of National Defence (DND), Canada Foundation for Innovation (CFI) and Ontario Research Funding for their support. We also acknowledge CMC Microsystems for providing access to fabrication foundries and design tools. BJS is supported by the Canada Research Chairs (CRC) Program.

Author contributions

A.K., C.H., A.N.T. and B.J.S. conceived the idea. A.K. performed the simulations, the layout of the chip, and carried out the experiments. A.K. and A.A. performed photodetector bandwidth measurements. A.N.T reviewed the layout. A.K. and A.A. wrote the manuscript. All co-authors analyzed and discussed the data and contributed to revising the manuscript. B.J.S. supervised this work.

Peer review

Peer review information

Nature Communications thanks Thomas Schneider, Christos Vagionas and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Data availability

The data generated in this study have been deposited in the Figshare database under accession code https://doi.org/10.6084/m9.figshare.30228727

Code availability

Codes used in this study are available from the corresponding authors upon request.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-025-66561-7.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

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