Primary Droop Current-Sharing Control of the Parallel DC/DC Converters System considering Output Cable Resistance

Abstract

This paper presents a primary droop current-sharing controller that can integrate into voltage feedback controller and, thus, provides a low-cost and simple solution for parallel DC/DC converters system. From the equivalent small-signal model, a two-port network was adapted to describe the output and control variables for designing voltage and droop current-sharing loops. From the analysis results, the designed primary droop current-sharing controller will not affect the original voltage loop gain profile to let the DC/DC converter preserve desire control performance. After designing a stable DC/DC converter with primary droop current-sharing control, the stability of the interconnected parallel DC/DC converters system was studied. When the cable resistance is reduced, when the cable resistance is reduced, the interconnected system might be unstable. Finally, some simulation and experimental results demonstrated the effectiveness of the proposed controller in a prototype parallel DC/DC converters system.

(ProQuest: ... denotes non-US-ASCII text omitted.)

Recommended by Francesco Profumo

Department of Electrical Engineering, Ching Yun University of Technology, 229, Chien-Hsin Road, Jung-Li 320, Taiwan

Received 7 December 2010; Accepted 9 February 2011

1. Introduction

In general, the server power system infrastructure consists of frond end AC/DC converters to build up high DC voltage and DC/DC converters to provide power to downstream load. The AC/DC converter uses power factor correction control to let the input line current meet the current harmonic specification; furthermore, the second-stage DC/DC converters and the interconnected cables construct a DC-distributed power system. A DC power system consists of many standard DC/DC converters through interconnected cables or copper buses in series or parallel to obtain desire output voltage, current, and power [1-4]. The structures of the interconnected DC power system have four topologies, that is, input series output series, input series output parallel, input parallel output series, and input parallel output series [2, 4]. The series structure can obtain high output voltage or withstand high input voltage; the kernel of the control strategy is to achieve voltage balance operation among the DC/DC converters. As to the parallel operation, high output current is the major advantage. However, the equal current-sharing control among each of DC/DC converters is the key performance index. In the server power system infrastructure, the parallel DC/DC converters system plays the key role to provide low voltage and high output current capability through the delicate designed interconnected system.

In order to obtain equal current-sharing control in the parallel DC/DC converters system, the current-sharing control should be designed. The most prevailing current-sharing control scheme is the active current-sharing control scheme, especially, the master slave and average current-sharing controls [5-10]. The literature [6, 7] provides the key theoretical study in the master slave and average current-sharing controls. However, the control system analysis of the droop current-sharing control seems to have little study. Most of the investigations focused on the steady-state droop voltage characteristics [11-18]. In addition, the interconnection of the DC/DC converters to form the parallel DC power system requires extra cable wires or copper buses. The study depicted suitable cable resistance can improve the stability of the parallel DC/DC converters system [19]. Furthermore, the common mode stability problem caused by the interconnected and system impedances was found in the paper [7]. The results showed the analysis and design method to obtain a stable interconnected system is to design a stable DC/DC converter and then to analysis the stability of the interconnected subsystem [20]. Finally, if the aforementioned analysis is stable, then the whole DC power system is also stable.

The major purposes of this paper are to design a controller that integrates the voltage and droop current-sharing controllers and to investigate the effects of the output cable resistance to the stability of the interconnected system. Firstly, the small signal model of the buck derived converter was derived in term of the two-port network. From the model reveals the cross-coupling effect was caused from the primary droop current-sharing control path. In order to preserve the voltage loop gain profile, the droop controller was proposed to reduce the parameter uncertainty of the DC/DC converter. After designing a stable DC/DC converter primary with droop current-sharing control, the final interconnected system was analyzed. This system consists of many cable wires to parallel connect the output voltages of the DC/DC converters to the system load. Using the circuit theory to analyze this interconnected system found the cable resistance might affect system stability. Through the investigation of a simple interconnected system, the phase margin will reduce when the cable resistance was reduced. In addition, the Spice-based circuit simulation further confirmed this phenomenon. Finally, the design methods of the droop voltage characteristics and controllers are provided in the appendix. Furthermore, some simulations and experimental results are used to demonstrate the aforementioned findings.

2. Modeling of a Parallel DC/DC Converters System with Primary Droop Current-Sharing Control

Figure 1(a) shows a parallel DC/DC converters system with primary droop current-sharing control which consists of N DC/DC converters, and the symbol i denotes the i th DC/DC converter for i=1 to N . The interconnection of the DC/DC converters system to load _zL is modeled as a resistor _rwi for i=1 to N . In addition, the notations _Voi and _Vo denote the output voltage of the i th DC/DC converter and actual load voltage. In order to clarify the voltage and primary droop current-sharing controllers, Figure 1(b) details the actual circuits implementation of the i th DC/DC converter, which is an interleaved dual switch forward converter (IDSFC) with one output inductor. Furthermore, the symbols _Vrefi , _Vi , n , _Ioi , and _Iii denote reference command setting, input voltage, transformer turn ratio, output current, and primary input current, respectively. The voltage controller integrates _Gc1 (s) and _Gc2 (s) controllers with the _Gdr (s) droop controller using a simple analog controller and thus provides a low-cost solution. The meanings of the controllers parameters can be comprehended by their notations. The low-pass filter _Gf (s) senses the primary input current and generates the designed droop voltage command _Vdr with respect to different load currents.

(a) The parallel DC/DC converters system; (b) the interleaved dual switch forward converter with primary droop current-sharing control.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

Figure 2(a) shows the equivalent small signal circuits of the i th DC/DC converter, where the nominal duty ratio, equivalent secondary voltage, and equivalent series resistances of output capacitor and inductor are D , _Vg , _rc , and _rL , respectively, and _Vg =_Vi /n [21]. Furthermore, the lower case symbols _vi , _di , _vg , _igi , _iii , and _ioi denote the small signal variables of the aforementioned uppercase notations. For a N parallel DC/DC converters system, the output current of the i th DC/DC converter _Ioi equals to _Io /N in an equal current-sharing operating condition, where _Io is the total load current, and, thus, the equivalent load resistance of each DC/DC converter is _Rn =_Vo /_Ioi for small signal analysis. The small signal model of the converter in Figure 2(b) shows that droop current-sharing control via sensing primary input current contains an extra current source, that is, _Ioidi . This current source shows an extra coupling effect between input current _iii and duty ratio _di . Neglecting the perturbation of the input voltage, the small signal model of the i th DC/DC converter is similar to a two-port network as shown in Figure 2(b) to be [figure omitted; refer to PDF] where input variables are _di and _ioi , and output variables are denoted as _voi and _iii , respectively. The key transfer functions used for analysis latterly list in the appendix. The detailed design and analysis are introduced as follow.

(a) The small signal model of the IDSFC; (b) the equivalent two port network.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

3. Parallel DC/DC Converters System Analysis and Design

3.1. Voltage and Droop Current-Sharing Loops Design

From Figure 2(b), the i th DC/DC converter includes the voltage feedback, and primary droop current-sharing controllers are shown in Figure 3(a); furthermore, Figure 3(b) is its equivalent control block diagram and suitable for control system analysis via signal flow method. As a result, the total loop gain of the i th DC/DC converter is [figure omitted; refer to PDF] [figure omitted; refer to PDF] [figure omitted; refer to PDF] where _Tv and _Tdr denote voltage and droop current-sharing loop gains, respectively. Let the droop current-sharing controller design as [figure omitted; refer to PDF] The gain constant _kd can deduce from Figure 1(b) to be _R2 /_R3 . Substituting (5) into (4), the total loop gain can be expressed as [figure omitted; refer to PDF] In order to preserve the original voltage loop gain profile and not to be affected by the droop current-sharing loop, the transfer function ΔW must meet the following criterion: [figure omitted; refer to PDF] After manipulating the transfer function ΔW , the denominators of the transfer functions _Hi and _Fdi can cancel so the resonant peak of the transfer function ΔW will not occur. Furthermore, the droop gain constant _kd and transformer turn ratio also contribute to let _||ΔW||∞ less than 1. Properly design the low-pass filter _Gf to let ΔW be proper, and the effect of the transfer function ΔW to voltage loop gain could be small. As a result, the transfer function ΔW can be regarded as parameter uncertainty of the plant. To reduce parameter uncertainty of the plant, the simple approach is to increase the gain margin of the DC/DC converter. If the gain margin is greater than 10 dB, the effect of the parameter variations in modeling error can reduce [6]. The great benefit of using the design droop controller depicted in (5) is that the voltage and droop current-sharing controllers can integrate and implement in a single operational amplifier as shown in Figure 1(b). The voltage controller shown in Figure 1(b) is a simple lead-lag controller _Gc (s) which consists of the controllers _Gc1 (s) and _Gc2 (s) , and can be expressed as [figure omitted; refer to PDF] where the poles and zeros of the voltage controller are _ωo1 , _ωp1 , _ωp2 , _ωz1 , and _ωz2 , respectively, and might be comprehended from (8). A simple pole placement method suggested in the literature [22], and the desired total loop gain can be approximated as [figure omitted; refer to PDF] where the pole _ωo designs to obtain desired bandwidth and phase margin; furthermore, the _ωp2 filters out the switching noise. The detail parameters of the integrated controller are listed in the appendix.

(a) The control block diagram of the i th DC/DC converter in parallel DC/DC converters system; (b) the corresponding block diagram of the i th DC/DC converter.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

3.2. Interconnected System Analysis

In general, the stable DC/DC converter can be designed by aforementioned pole placement scheme shown in (8). When a lot of stable DC/DC converters are paralleling operation, the interconnection of the DC/DC converters to actual load forms an interconnected system. In the following analysis, the Thevenin theorem and signal flow method were used. From Figure 3(b), the feedback output impedance of the DC/DC converter is [figure omitted; refer to PDF] Obviously, the feedback output impedance of the DC/DC converter with primary droop current-sharing control is discrepant to original feedback output impedance. In fact, the primary droop current-sharing loop affects the feedback output impedance. Furthermore, the transfer function from reference command setting _vrefi to output voltage _voi can be deduced as [figure omitted; refer to PDF] Then, the equivalent Thevenin small signal model of the parallel DC/DC converters system is showed in Figure 4. Using node analysis at output node, the relations of the output current _ioi to reference command _vrefi of each DC/DC converter for i=1,...,N are [figure omitted; refer to PDF] The aforementioned matrix in (12) is nonsingular so its inverse matrix exists. Using matrix inversion formula (^(D-CE)-1 =^D-1 +^D-1 C^{(I-ED-1 C)-1} E^D-1 ), the output current _ioi is [figure omitted; refer to PDF] where [figure omitted; refer to PDF] If the parameters of the DC/DC converters are identical and symmetric layout interconnected system is designed, that is, the cable resistance is identical. In this condition, The reference command setting _vrefi of the i th DC/DC converter is perturbed by _v...refi , and the resulted output current perturbation _i...oj for j=1,...,N is [figure omitted; refer to PDF] where _zj =z , j=1,...,N . In general, the transfer function _Fi is stable, and if the zeros of the denominator of (14) locate at on left half plane, then the parallel DC/DC converters system is stable. The aforementioned method can be applied to other DC/DC converters like boost converter for example.

Figure 4: The Thevenin equivalent parallel DC/DC converters system.

[figure omitted; refer to PDF]

4. Simulation and Experiment

Obviously, from (12) to (15), it is very difficult to find the effect of the output cable resistance to system stability. In order to clarify this, an interconnected system equips with two DC/DC converters is analyzed in detail. From Figure 3, one can construct the control system block diagram of the interconnected system as shown in Figure 5(a). Using (9) to (13), the cross coupling effects of the interconnected system depicts in Figure 5(b). The loop gain of the interconnected system is [figure omitted; refer to PDF] where [figure omitted; refer to PDF] If the parameters of the DC/DC converters are identical and symmetric layout of the interconnected system is designed, (16) can be deuced as [figure omitted; refer to PDF] Substituting the parameters of the IDSFC into the transfer functions _Fdi and _Aii , the resulted frequency responses are demonstrated in Figure 6. It shows the magnitude of the transfer function _Fdi is always above 0 dB due to the extra current source in the small signal model. In addition, the profile of the transfer function _Aii is similar to the transfer function _Hi with lower gain. Figure 7 depicts the voltage, droop current sharing, and total loop gains and the parameter uncertainty ΔW . One may find _||ΔW||∞ is -9.91 dB at 40.9 KHz and meets the criterion (7) so the effect of the parameter uncertainty is minimized. Therefore, the profiles of the three loop gains are quite similar with different offset. Using the proposed design droop controller in (5), the total loop gain is not affected by the primary droop current-sharing control significantly. The gain and phase margins of the DC/DC converter can be preserved and gained a stable operation. Figure 8 shows the discrepancy of the open-loop and feedback output impedances. It is interesting to find that the feedback output impedance _zofi is greater than output impedance _zoi in low frequency range. However, the feedback output impedance _zofi is rolled off as frequency increased and does not have resonant peak phenomenon. In order to clarify the effects of the output cable resistance to stability, two different cable resistances were simulated in the interconnected system loop gain as shown in Figure 9. When the cable resistance is reduced from 1 mΩ to 0.1 mΩ, the magnitude of the interconnected system loop gain _Tzloop is shifted up and leads to reducing phase margin of the system. From the simulation results, the magnitude and phase were not affected either resistance load or paralleling extra 10000 μ F capacitance load. In this simulation case, the phase margin is 70° with _rwi =1 mΩ, but when the cable resistance was reduced to 0.1 mΩ, the phase margin is almost vanishing. In order to further find the effects of the output cable resistance, a Spice-based simulation was carried out via Simetrix/Simplis. Figure 10 shows the output current response of the step referent command disturbance in the 1 mΩ and 0.1 mΩ cases. Figure 9(a) depicts the output currents can subside back into equal current-sharing control in 1 mΩ cable resistance case; unfortunately, Figure 10(b) shows the unstable operation via 0.1 mΩ cable resistance. This conforms the previous comments that a large cable resistance can improve the system stability [19].

The parallel DC/DC converters system with N=2 interconnected system: (a) detail control block diagram and (b) simplified diagram.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

The frequency responses of the _Fdi and _Aii transfer functions at half load current operation: (a) magnitude; (b) phase.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

The frequency responses of the transfer functions _Tv , _Tdr , _Tv +_Tdr , and ΔW at half load current operation: (a) magnitude and (b) phase.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

The frequency responses of the opened- and closed-loop output impedances of the DC/DC converter at half load current operation: (a) magnitude and (b) phase.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

The frequency responses of the parallel DC/DC converters system with output cable resistances 1 mΩ and 0.1 μ Ω at half load current operation: (a) magnitude and (b) phase.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

The step reference command disturbance of the parallel DC/DC converters system with different output cable resistances at full-load current operation: (a) 1 mΩ and (b) 0.1 μ Ω.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

After the simulations have demonstrated the performance of the proposed integrated controller for voltage and droop current-sharing control, the paralleled DC/DC converter system with N=2 was implemented. Furthermore, The PWM IC UC3525 was used to generate two-phase PWM pulses to control IDSFC as shown in Figure 1(b). Figure 11(a) shows the measured primary currents and MOSFET drain to source voltage waveforms for referent. It shows the primary currents of the two forward converters are in balance operation. Owing to one output inductor scheme, two power trains of the IDFSC have the same primary side current, which reflects from the secondary side inductor current as shown in Figure 11(b). Furthermore, the hot swap operation is also depicted in Figure 11(c), the parallel IDFSCs can achieve equal sharing control. Figure 12 shows the loop gain profiles of the IDFSC, which are similar to the simulation results. It shows the designed IDFSC has at least 45° phase margin, 10 dB gain margin, and 10 KHz bandwidth; therefore, the effects of the parameter uncertainty can reduce significantly. Because the cable length of the prototype IDFSC is 30 cm with 2 mΩ resistance as shown in Figure 13(a), the resulted interconnection system is stable. The physical size of the IDFSC and interconnected system can let the cable length be shorted to 15 cm, and the resulted cable resistance is 1 mΩ as depicted in Figure 13(b). However, it is very difficult to obtain 0.1 mΩ cable resistance in this laboratory prototype interconnected system to demonstrate the unstable operation. Fortunately, from the theory study and simulation verification, the cable resistance will affect system stability.

The key waveforms of the parallel DC/DC converters system at full-load current operation: (a) primary current and primary MOSFET drain to source voltage of the IDSFC; (b) the current and the input voltage of the output inductor; (c) hot swap operation.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

(c) [figure omitted; refer to PDF]

The measured _Tv and _Tv +_Tdr frequency responses of the IDSFC at full-load current operation: (a) magnitude and (b) phase.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

(a) The photograph of the IDSFC with 2 mΩ output cable resistance; (b) the back plane system with N=2 and the corresponding connected output cables.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

5. Conclusions

An interconnected DC power system consists of DC/DC converters with primary droop current-sharing control was presented in this paper. Using the proposed droop controller will not affect the original design voltage loop gain profile but also can integrate into voltage controller and thus provides a low-cost solution. Furthermore, after a stable DC/DC converter design was achieved, the effect of the cable wire resistances of the interconnected system to stability was also investigated. The results demonstrated that the reduction of the cable resistance will decrease the phase margin of the interconnected system and lead to instability. Properly increasing the cable resistance can improve system stability, but the operating efficiency will reduce. This paper provides a method to evaluate the stability of the interconnected system. Using this method, the engineer can make a tradeoff between system stability and efficiency.

Table 1

R1	R2	R3	R4	R5	R6	C1	C2	C3	C4
2.57 kΩ	10 kΩ	100 kΩ	1 kΩ	33 kΩ	10 kΩ	4700 pF	6800 pF	680 pF	220 pFx2

Table 2

Rf1	Rf2	Cf1	Cf2	kf
1 kΩ	100 Ω	0.1 μ F	0.01 μ F	2.4

Acknowledgment

The authors thank the National Science Council of Taiwan for supporting the research project: NSC99-2221-E231-036.

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Appendix

Appendix

(1) The Designed Parameters of the Interleaved Dual-Switch Forward Converter Are as Follows.

(i) Primary side DC bus voltage _Vi =385 V.

(ii) Primary switching frequency _fs =125 kHz.

(iii): Nominal output voltage _Vo =12 V.

(iv) Nominal output current _Io =66 A.

(v) Transformer PQ32/30 _NP =20 turns, _Ns =1 turn, and n=20 .

(vi) Output inductor MS10675 with inductance L=2 μ H.

(vii): Output capacitance C=5400 μ F and esr=4 mΩ.

(viii): Nominal duty ratio D=0.62 in the secondary side of the IDSFC with an output inductor.

(ix) The gain of the PWM comparator K=0.25 .

(2) The Key Transfer Functions of the IDFSC

[figure omitted; refer to PDF] where [figure omitted; refer to PDF]

(3) Design Procedure of the Steady-State Output Voltage Droop Characteristic

In general, the output voltage droop characteristic of a DC/DC converter depends on output voltage regulation specification with a predetermined design margin. If the maximum, nominal, and minimum output voltages of the regulation range are denoted as _Voi,max , ^Voi* , and _Voi,min , respectively. From Figure 1(b), the output voltage variation of the i th DC/DC converter with respect to droop current-sharing control is [figure omitted; refer to PDF] where [figure omitted; refer to PDF] [figure omitted; refer to PDF] Furthermore, the droop voltage _Vdr synthesizes from primary current through a low-pass filter, which is proportion to output current, that is, _Iii =D_Ioi /n . From (A.3) and (A.4), the output voltage deviation Δ_Voi can be expressed in terms of droop voltage as [figure omitted; refer to PDF] For a given output voltage deviation Δ_Voi , the design procedure of the output voltage droop characteristics is suggested as follows.

(i) Let ^{R1[variant prime]} =k_Vrefi and k>0 .

(ii) The resistance _R2 can subsequently be determined from the maximum output voltage listed in (A.3), _Kd , and ^{R1[variant prime]} .

(iii): For a given specification of the output voltage deviation and droop voltage, the resistances _R1 and _R3 can be found from (A.6) and resistance ^{R1[variant prime]} .

(4) Voltage and Primary Droop Current-Sharing Controller

The feedback controllers in Figure 1(b) are [figure omitted; refer to PDF] where [figure omitted; refer to PDF]

(i) The design poles and zeros of the controller _Gc1 (s) , _Gc2 (s) , and _Gdr (s) can let the DC/DC converter have at least 45° phase margin, 10 dB gain margin, and 10 KHz bandwidth [figure omitted; refer to PDF]

(ii) Circuit parameters of the controller _Gc1 (s) , _Gc2 (s) , and _Gdr (s) ; (see Table 1).

Note

(1) Using the nearest commercial parts instead of the estimated parameters.

(5) Low-Pass Filter _Gf (s)

[figure omitted; refer to PDF] (see Table 2).