A Capacitive Feedback Transimpedance Amplifier with a DC Feedback Loop Using a Transistor for High DC Dynamic Range

Abstract

This study proposes a capacitive feedback transimpedance amplifier (CF-TIA) using a transistor in the direct current (DC) feedback loop for high DC dynamic range. In some applications, the background DC input can vary widely from the minimum to the maximum, and TIA have to sense the target signal even on the top of the maximum DC input. In a conventional CF-TIA, however, the allowable DC input is constrained by the value of the resistor in the DC feedback loop. To allow a fairly high DC input, the resistor is set to a very low value. This causes the thermal noise current to increase significantly. The increased thermal noise is always present even in the minimum DC input, thus degrading the overall noise performance. The circuit proposed herein overcomes this shortcoming by using the transistor instead of the resistor. The adverse effect of the parasitic capacitance of the transistor on system stability is compensated for as well. Then, the analyses of the overall frequency response and design parameters, including the cut-off frequency and attenuation ratio associated with system stability, are presented for the proposed circuit. In addition, in order to cope with the problem that stability is dependent on the amount of DC input, a simple method for ensuring system stability regardless of DC component value is introduced. The presented analyses and the method are generalized for all CF-TIA applications.

1. Intoroduction

Precision instrumentation systems, such as optical receivers [1], electrical sensors [2,3,4,5], emerging biosensors [6,7,8] photodetectors [9,10,11], and other current-output measurement systems, often contain a transimpedance amplifier (TIA). An operational amplifier (op-amp) with negative feedback is typically used in a TIA. The most typical TIA topology is a resistive feedback TIA (RF-TIA), which is simple and easy to analyze as the feedback resistor directly matches the transimpedance gain. In [3,4,6,7,12,13,14,15], a capacitive feedback TIA (CF-TIA) has been proposed to reduce the thermal noise generated by the feedback resistor, as well as overcome difficulties in the integration of high resistance in complementary metal-oxide-semiconductor (CMOS) chips.

The basic topology of the CF-TIA is composed of an integrator and a cascaded differentiator, as shown in Figure 1. The DC feedback loop is typically inserted in the first stage integrator. It provides a DC path to prevent saturation of the integrator’s feedback capacitor_Cfand simultaneously to bias the op-amp. The conventional DC feedback loop consists of an non-inverting integrator to filter the DC components on the feedback path and a resistor_Rdcto drain the DC components from the input node. Although a high value of_Rdcis preferred to reduce the thermal noise currents of_Rdc , it limits the maximum allowable DC input with the output voltage range of the op-amp, as in [6,7]. The voltage drop across_Rdcwith the DC input should be less than the op-amp output voltage range which is usually slightly less than the op-amp supply voltage. The higher the allowable DC input, the lower the value of_Rdc.

In some applications such as optical sensors, the DC input varies according to the amount of background light. While the normal DC input from the ambient light is typically low, the maximum feasible value of the DC input can be fairly high when intense light is directly incident on the sensors. The TIA has to sense the weak target signal on top of the expected maximum value of the DC input in the worst case scenario. However, to allow for high DC input, the value of_Rdcshould be very low, causing the thermal noise to increase significantly. To make matters worse, increased thermal noise is always present even at normal or low DC inputs, degrading overall system performance. In this study, to overcome the shortcomings of the conventional CF-TIA, a new topology that replaces_Rdcwith the transistor in the feedback loop is introduced. The method of discharging DC inputs using the transistor in the DC feedback loop is one of the widely used methods in various circuits, but it has not yet been used and analyzed for CF-TIA. With the transistor, the high DC can flow with a much smaller voltage drop across the base-emitter (gate-drain) compared to the significant voltage drop that occurs when a resistor is used. The thermal noise of the resistor is then replaced by the shot noise of the transistor.

Actually, when assuming a constant DC input, the shot noise is larger than the thermal noise. However, if the DC dynamic range, i.e., the range from the minimum to maximum DC, is significant, the proposed topology has the benefits in the overall noise. The shot noise of the proposed topology varies with the amount of the DC input. In normal cases, DC inputs are much less than the maximum value, so the proposed topology can exhibit lower noise than conventional topology that always shows the worst thermal noise to cope with maximum DC inputs. The advantage in terms of the noise is more distinct compared to the CMOS implementation of the conventional CF-TIA where the thermal noise and shot noise coexist for the pseudo-resistor [6,7]. For the CMOS implementation, the proposed topology shows the lower noise than the conventional topology by the amount of thermal noise even for the maximum DC input.

The proposed circuit includes a method for compensating for the adverse effect of the parasitic capacitance of the transistor on system stability. The overall frequency response and design parameters, such as the cut-off frequency and attenuation ratio associated with the system stability, are presented and analyzed for the proposed topology. Moreover, the inclusion of an additional capacitor to the DC feedback loop for ensuring system stability regardless of the DC input value is discussed. Through simulations and experiments, the proposed CF-TIA scheme is validated. In this study, the circuit is implemented with discrete components, but the frequency response model and stability analysis presented are generalized to be applicable to all CF-TIA applications and CMOS chip designs. 2. CF-TIA with DC Feedback Path Using Transistor

This section investigates and analyzes the proposed CF-TIA using a transistor in the DC feedback loop shown in Figure 2. The transistor_Tdcserves as a variable current sink that pulls the average DC input_Idcfrom the signal path under a steady state condition. Note that the high current can flow from the collector (drain) to the emitter (gate) with only a low base-emitter (gate-drain) voltage.

First, the fundamental performance of the CF-TIA is presented. The achievable bandwidth of the CF-TIA or the upper cutoff frequency,_fH, is limited by the gain-bandwidth product of the op-amp_fGBWPand the ratio between_Cfand_Cin as follows [6,7]:

_fH≤_fGBWP·_CfCin+_Cf,

where_Cin=_Cs+_Ci,op+_Cμ+_Cμ,cis the total capacitance at the TIA input including the sensor capacitance_Cs, the input capacitance of the op-amp_Ci,op(encapsulating the differential and common mode capacitance), the base-collector (gate-drain) parasitic capacitance of the transistor_Cμ, and the capacitor_Cμ,cto compensate the effect of_Cμ.

Following this, the overall flat gain of the generic CF-TIA can be described as follows:

_{vo iin}=_{Cd RdCf},

where_Cdand_Rdconstitute the second differentiator,_iinis the input current, and_vois the output voltage of the CF-TIA. Because the gain of the differentiator increases with the frequency until it is rolled off by the open-loop gain of the op-amp, the product of_Cdand_Rdis constrained as follows:

_{Cd Rd}≤_fGBWP2π_fH2.

Note that while both a bipolar junction transistor (BJT) and a field-effect transistor (FET) can be used as_Tdc, the FET shows a higher parasitic capacitance_Cμ than that of the BJT, resulting in a reduced bandwidth as in (1). Thus, we use the BJT for_Tdchere. Then, in order for_Tdcto be in an active mode, the appropriate emitter voltage_VEmust be set such that the collector-emitter voltage is greater than 0.7 V. Moreover, to compensate for the influence of_Cμon system stability, the inverting amplifierG(s)whose overall gain is−_Gc, and the capacitor_Cμ,care inserted between the collector and the base of_Tdc.

A detailed analysis of the frequency response of the proposed CF-TIA is presented in next. Applying Kirchhoff’s current law at the negative input node of the integrator gives [16]:

_iin=s_Cfv−−_vi,o+s_{Cs v−}+_v−−_vi,os_{C1 R1}s_Cμ+_v−−_Gcvi,os_{C1 R1}s_Cμ,c=(a)−_vi,os_Cf+_Cs+_Cμ+_Cμ,cA(s)+s_Cf+_{Gc Cμ,c}−_{CμC1 R1}+_gms_{C1 R1}≈(b)−_vi,os_Cf+β_{C1 R1}+_gms_{C1 R1}

where_vi,ois the output voltage of the first stage integrator,A(s)is the open-loop gain of the op-amp,_gm=_Idc/_VTis the transconductance of_Tdc,_Idcis the DC input,_VTis the thermal voltage (approximately 25 mV at a room temperature of 259 K),_C1and_R1constitutes the integrator in the DC feedback loop, andβ=_{Gc Cμ,c}−_Cμ . In (4), (a) follows from substituting_v−as−_vi,o/A(s), and the approximation (b) follows from thatA(s)is exceedingly high within the system bandwidth.

By rewriting (4) to the transimpedance gain form, the transfer function of the integrator_Hi(s)is obtained as follows:

_Hi(s)=_{vi,o iin}≈−1_Cfs^s2+βs_{C1 R1 Cf}+_{gmC1 R1 Cf},

Rewriting (5) to a standard form of the transfer function of a second-order bandpass filter with a center frequency_w0and a damping ratioζ(=1/(2Q))yields:

_Hi(s)=−_{C1 R1}β2ζ_w0s^s2+2ζ_w0s+_w02

where_w0=2π_f0,

_f0=12π_{gmC1 R1 Cf}andζ=β2_{gm C1 R1 Cf}.

Now, we obtain the upper and lower cut-off frequencies,_fi,Hand_fi,Lof_Hi(s). From the fact that_f0is the geometric mean of_fi,Hand_fi,L , and from (5), followings are derived:

_fi,H·_fi,L=^12π2_{gmC1 R1 Cf}and_fi,H+_fi,L=β2π_{C1 R1 Cf}.

When the wide passband is assumed as_fi,H≫_fi,L,_fi,H+_fi,L≈_fi,H. Thus,_fi,Hand_fi,Lcan be expressed as follows:

_fi,H=β2π_{C1 R1 Cf}and_fi,L=_gm2πβ.

Moreover, from the assumption of wide passband byζ≫1/2,_fi,H≫_fi,Lis proved, expressed as

β2π_{C1 R1 Cf}≫_gmπβ>_gm2πβ.

From the expressions forβand_Hi(s) in (5), it can be observed that both_Gcand_Cμ,censure the circuit stability. In the absence of_Gcand_Cμ,c,βbecomes negative, resulting in two positive real poles in_Hi(s). If the system has any poles with a positive real part, the part of outputs diverges without a bound, causing system instability. The value of_Cμ,c is preferred to be negligibly small relative to the total input capacitance in order to maximize the achievable bandwidth as in (1).

In terms of stability,_Gcis preferred to be high, so that makes the system free of gain peaking asζ≥1/2, even with the high_gm. Note that we assume that the stability is determined based on a condition of a maximally flat response (Butterworth response), which isζ=1/2. However,_Gcis limited by the condition that the first pole frequency ofG(s)should be placed above_f0. Note that_f0varies with_Idc, and the case when_f0exceeds the system bandwidth_fHis not taken into account. The aforementioned discussion suggests the following conditions:

_Cμ,c≪_Cinand_Gc≤_{fGBWP fH}.

By cascading the differentiator to the integrator, the overall CF-TIA transfer function,H(s), is derived by multiplying_Hi(s)by the differentiator transfer function as follows:

_Hd(s)=_{Rd R2}1+s_{Cd R2}1+s_{Cc Rd},

where_Ccis used to stabilize the differentiator as_Cc=1/2π_{Rd fH}, and_R2is placed parallel to_Cdin order to generate a zero in_Hd(s)at_fi,H in (9) such that_{Cd R2}=_{C1 R1 Cf}. Then, the flat gain of_Hi(s)is multiplied by_Rd/_R2, and the decrease in_Hi(s)beyond_fi,His compensated by the increase in_Hd(s)with the introduced zero. The resultingH(s)becomes the bandpass filter transfer function, whose lower cutoff frequency_fLis equal to_fi,L._Hi(s),_Hd(s),andH(s) are shown in Figure 3 for increasing_Idcfrom 10 pA to 10 uA. Note that as_Idcincreases,ζdecreases. Eventually, a gain peaking occurs, as shown for_Idc=10 uA in Figure 3.

We can include the additional capacitor_C2parallel to_R1to ensure stability, regardless of the_Idcvalue. In the presence of_C2 , following the approaches in (4) and (5) gives_Hi(s)as

_Hi(s)≈−1(1+γ)_Cfs^s2+11+γβ_{C1 Cf R1}+γ_gmβs+_gm(1+γ)_{C1 Cf}R1,

whereγis the parameter that controls the value of_C2and system stability, such thatβ_C2=γ_{C1 Cf}. The design parameters are then described as follows:

_f0=12π_gm(1+γ)_{C1 R1 Cf}and

ζ=121+γβ_{gm C1 R1 Cf}+γ_{gm C1 R1 Cf}β.

Then, the upper and lower frequencies of_Hi(s)are expressed in two cases depending on the amount of_Idc. The first case is for a low_Idcwith_gm≪^β2/(γ_{C1 Cf R1}), and

_fi,H=β2π(1+γ)_{C1 R1 Cf}and_fi,L=_gm2πβ.

The second case is for a high_Idcwith_gm≫^β2/(γ_{C1 Cf R1}), and

_fi,H=γ_gm2π(1+γ)βand_fi,L=β2πγ_{C1 R1 Cf}.

Notably,_R2is placed to generate a zero in_Hd(s)at_fi,H of (16) as previously discussed.

Eventually, multiplying_Hd(s) of (12) to_Hi(s) of (13) rendersH(s)to the bandpass filter frequency response whose lower cutoff frequency is expressed as follows:

_fL=_gm2πβ,_gm≪^β2/(γ_{C1 Cf R1})γ_gm2π1+γβ,_gm≫^β2/(γ_{C1 Cf R1}).

Note that the inclusion of_C2reduces the overall flat gain magnitude by a factor of1+γ. To achieve the same flat gain magnitude that is exhibited when_C2is not included, either_Rdor_Cdshould be multiplied by1+γ. From the arithmetic-geometric mean inequality,ζ of (14) has a lower bound of the following:

ζ≥γ1+γ,

where equality holds when_gm=^β2/(γ_{C1 Cf R1}). Forγ=1, the stability is always ensured byζ≥1/2, regardless of the_Idc value, as in Figure 4.

Noise performance analysis is presented in the remaining part of this section. The input-referred noise model is commonly used in noise analysis for comparing input signals and noise levels. In this topology, instead of the thermal noise of the resistor, the current noise of the transistor,_iTR , is added to the typical root mean square (RMS) value of the input-referred noise expression of [17] as follows:

_iN.rms=_in2+_iTR2+^{_en2π_fcCs+β2}3.

where_inis the inverting-input current noise of the op-amp, and_enis the differential voltage noise of the op-amp. The noise_iTRis the shot noise of_Tdc, where_iTR2≈2q_Idcand q(=1.6e−19)is the electron charge. Note that a flicker noise can be significant when implementing circuits with CMOS technology or using MOSFET instead of BJT in_Tdc . However, the flicker noise can be made negligible when assuming the broad range of signal bandwidth and using a non-minimal MOSFET area [4].

The proposed CF-TIA shows better overall noise performance compared to that of the conventional CF-TIA when the dynamic range of_Idcis wide. For example, assume that the dynamic range of_Idcis 30 dB from 100 nA (normal_Idc) to 100 uA (the expected maxima value of_Idc). Because of the maximum_Idc,_Rdcof the conventional CF-TIA is constrained to 50 kΩ(=_Vs/100 uA)where the supply voltage_Vsis 5 V. The maximum output voltage of the op-amp is assumed to be same as the supply voltage. Then, the thermal noise current of_Rdcbecomes 1 pA/Hz(=4kT/_Rdc)where k (=1.38e−23J/K) is the Boltzmann constant and T (=300 K) is the absolute temperature.

This thermal noise current always exists even in normal_Idcdegrading the overall noise performance. However, in the proposed CF-TIA, thermal noise current of the resistor is eliminated and the shot noise of a normal_Idc(=100 nA) becomes 0.17 pAHz(=2q_Idc), which is much lower than the thermal noise current of 1 pA/Hz.

Furthermore, the noise of the proposed circuit is always less than that of the conventional CF-TIA implemented with CMOS, as in [6,7], in which the thermal noise and shot noise currents coexist. If the conventional CF-TIA is implemented with CMOS technology, the feedback resistor is implemented as a pseudo resistor with MOS devices. Therefore, the input-referred noise expression of conventional CMOS CF-TIA includes not only the thermal noise of feedback resistor, but also the shot noise of the MOS [7]. However, (20) has only the shot noise term without the thermal noise term.

Note that hereβ is associated with the noise contribution of the input capacitance term, the third term in (20). Both the influence on the total noise and the overall system stability should be considered together when determining_Gc.

3. SIMULATION and EXPERIMENT

The presented circuits were implemented and simulated using PSpice to verify the presented analyses of the transfer functions and design parameters. A photograph of the realized circuit is presented in Figure 5. All the circuits were built using the same op-amp (OPA657, Texas Instruments). OPA657 has wideband and low-noise characteristics, and its_fGBWPis 1.6 GHz,_Aolis 75 dB at room temperature, and_Ci,opof 5.2 pF. It is to be noted that_fGBWPis not a trimmed parameter and can vary by the maximum±40% due to the process variation for any op-amp [18]. Consequently, even though the datasheet specifies the_fGBWPto be 1.6 GHz, I have considered_fGBWPto be 1.28 GHz, about80%of this typical value in order to account for process variations.

Note that to compare the simulation, experiment, and analytic results, all values of the discrete components were set equivalently as the assumed values in the analytical example shown in Figure 4. Several variables were set by considering the laser position sensor application and its practical implementation. For the laser position sensor QP154-Q (First Sensor),_Csis assumed to be 20 pF. Taking the lowest value of the practical discrete capacitor,_Cfis set to 0.2 pF. By using MMBT5179 NPN transistor (On Semiconductor) with low parasitic capacitance,_Cμis set to 1 pF. The_Cd value has an upper limit of approximately 1 nF because of the capacitive loading effect at the OPA657 output. In addition, Figure 6 shows an example of the implementation ofG(s)for the simulation and experiment._RG,3and_CGrender the amplifier AC coupled to prevent_vG,o from being saturated with DC components. Given the aforementioned assumptions, the maximum achievable bandwidth was calculated as 9.3 MHz using (1), and overall flat gain magnitude was determined to be5E+6 from (2).

To assess the stability, the magnitude and phase of the loop gain were obtained through simulation, and plotted in Figure 7. Figure 7 shows the magnitude and phase of the loop gain of the integrator, depending on the presence or absence of_C2. For low_Idc, although the phase at low frequencies is about −180°, the stability is ensured by a high gain margin. At high frequencies, the phase drops from −180°, resulting in a very high phase margin at the gain crossover point where the magnitude of the loop gain reaches unity-gain (0 dB). However, as_Idcincreases, the point at which the phase begins to drop increases significantly. Eventually, for_Idc= 10 uA in Figure 7a, the phase margin is meager at 6.5°, causing the system to become unstable. This result is consistent with the analysis result shown in Figure 3, where the gain peaking occurs with_Idc=10uA. In the presence of_C2, the zero is added before the gain crossover frequency. Thus, we can ensure enough phase margin with_C2. For_Idc= 10 uA in Figure 7b, the phase margin becomes 135°. This result is also consistent with the analysis result shown in Figure 4, where the gain peaking is prevented on the presence of_C2with_Idc=10uA.

The frequency responses of the simulation and results of the experiment are shown in Figure 8. The experimental results strongly agree with the simulation results as well as the analytical results of Figure 4. The only difference is that the experimental results start to roll off at about_fH, slightly lower than the roll-off point of simulation results. There can be several reasons why this roll-off point in the measurement results is lower than that in the simulation results, such as additional input capacitance in the PCB layout and variations in the parameters of the circuit components. The major reason appears that the_fGPWP of the op-amp used in the actual implementation is less than the ideal values recorded in the datasheet or the simulation model parameters due to the process variation [16].

4. Conclusions In this study, a CF-TIA with a transistor in the DC feedback loop is proposed and analyzed for high DC input dynamic range. Our system avoids the shortcoming of the conventional CF-TIA, whereby the thermal noise for the maximum DC input always present even in normal or low DC input cases. In the proposed circuit, the thermal noise is replaced by the shot noise varying with DC input. Thus, the proposed circuit can have the benefit in overall noise performance for normal or low DC inputs. Moreover, the proposed circuit compensates for the adverse effect of the parasitic capacitance of the transistor, which would otherwise lead the system to diverge with a positive real pole in the frequency response. The overall frequency response and design parameters, such as the cut-off frequency and attenuation ratio associated with system stability, are analyzed providing useful guidelines for the proposed CF-TIA design. Furthermore, a method that avoids gain peaking, regardless of the DC input, is introduced. The proposed CF-TIA and its analyses are validated by the excellent agreement between the analyses, simulation, and experimental results. The proposed circuit and its analyses are not limited to a specific application. They can be applied to various sensor measurements, such as emerging bio-sensors, nuclear science instrumentation, and optical receivers, and their CMOS chip design implementations.

Figure 1. Capacitive Feedback Transimpedance Amplifier with conventional DC feedback loop.

Figure 2. Capacitive Feedback Transimpedance Amplifier with the proposed DC feedback loop with a transistor.

Figure 3. Transfer functions of the integrator, differentiator, and the overall system withoutC2forIdc=10pA, 100 nA, 1 nA, and 10 uA, whereCμ=1pF,Cμ,c=1pF,Gc=50,Cf=0.2pF,Cd=1nF,Cc=8.51pF,Rd=2kΩ,R2=8.16kΩ,C1=10nF, andR1=100kΩ.

Figure 4. Transfer functions of the integrator, differentiator, and overall system placingC2=40.8pF such thatγ=1forIdc=10pA, 100 nA, 1 nA, and 10 uA, whereCμ=1pF,Cμ,c=1pF,Gc=50,Cf=0.2pF,Cd=1nF,Cc=8.51pF,Rd=2kΩ,R2=8.16kΩ,C1=10nF, andR1=100kΩ.

Figure 5. Hardware Implementation.

Figure 6. Implementation ofG(s). The values of the discrete components areRG,1=1 Ω,RG,2=50 Ω,RG,3=1 MΩ, andCG=1uF.

Figure 7. Simulation of integrator's loop gain.

Figure 8. Simulation and Experimental result.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

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