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Abstract
Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. However, architectural research in the area of specialization architectures is still in its preliminary stages. A major obstacle for such research has been the lack of an architecture-level infrastructure that analyzes and quantifies the benefits and trade-offs across different designs options. Existing accelerator design primarily relies on creating Register-Transfer Level (RTL) implementations, a tedious and time-consuming process, making early-stage, design space exploration for specialized architecture designs infeasible.
This dissertation presents the case for early-stage, architecture-level design method- ologies in specialized architecture design and modeling. Starting with workload characterization, the proposed ISA-independent workload characterization approach demonstrates its capability to capture application’s intrinsic characteristics without being biased due to micro-architecture and ISA artifacts. Moreover, to speed up the accelerator design process, this dissertation presents a new modeling methodology for quickly and accurately estimating accelerator power, performance, and area without RTL generation. Aladdin, as a working example of this methodology, is 100× faster than the existing RTL-based simulation, and yet maintains accuracy within 7% of RTL implementations. Finally, accelerators are only part of the entire System on a Chip (SoC). To accurately capture the interactions across CPUs, accelerators, and shared resources, we developed an integrated SoC simulator based on Aladdin to enable system architects to study system-level ramifications of accelerator integration.
The techniques presented in this thesis demonstrate some initial steps towards early-stage, architecture-level infrastructures for specialized architectures. We hope that this work, and the other research in the area of accelerator modeling and design, will open up the field of specialized architectures to a wider range of researchers, unlocking new opportunities for efficient accelerator design.