Graphene radio frequency receiver integrated

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Received 2 Oct 2013 | Accepted 10 Dec 2013 | Published 30 Jan 2014

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without signicantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplication, ltering and down-conversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metaloxidesemiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

DOI: 10.1038/ncomms4086

Graphene radio frequency receiver integrated circuit

Shu-Jen Han1, Alberto Valdes Garcia1, Satoshi Oida1, Keith A. Jenkins1 & Wilfried Haensch1

1 IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Yorktown Heights, New York 10598, USA. Correspondence and requests for materials should be addressed to S.-J.H. (email: mailto:[email protected]

Web End [email protected] ).

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With recent developments in graphene eld-effect transistors (GFETs) showing intrinsic unity current gain frequencies (fT) higher than 400 GHz (ref. 1),

along with theoretical work projecting operation exceeding 500 GHz (ref. 2), graphene shows great promise in radio frequency (RF) applications. The rapid advances in graphene transistor performances, fT and maximum oscillation frequency (fMAX), came from all aspects of the device, including improved starting graphene materials3, better gate dielectrics46, improved contact resistance7, new device architectures8,9 and aggressive channel length scaling1,10. On the other hand, the pace of the development of graphene RF circuits seems signicantly slower, and raises the question about the true feasibility of using graphene in modern communication systems. Most graphene circuits demonstrated today are arguably the extension of the study of a transistor itself. High-performance discrete passive components have been connected to GFET externally at the equipment level, and these circuits are limited to single-transistor designs. Demonstrations using this approach have shown several promising GHz functions such as voltage amplication11, frequency multiplication12,13 and signal mixing7,14. However, to compete with existing technologies, particularly silicon, requires that all active and passive components be monolithically integrated onto single chip for not only the small circuit footprint and low cost but also high circuit complexity and advanced system functionality. A millimetre-wave mixer integrating exfoliated graphene and microstrip technology has recently been demonstrated15. The circuit fabrication, however, requires more exotic processes such as substrate thinning and through-substrate via etching. For the large-scale synthesized graphene, perhaps the best attempt displayed to date is a single-stage mixer integrated circuit (IC) built by small-piece, ofine-type processes16. This proof-of-concept IC consists of only one transistor, fabricated by a conventional process ow, that is, the active device was rst constructed, followed by a series of back-end-of-line (BEOL) processes to complete the circuit interconnect and passive components. Because of the delicacy of graphene, resulting from its single atomic layer nature and weak adhesion between graphene and other materials, these BEOL processes inevitably deteriorate GFET quality, which is evident from much worse device performance in the IC compared with stand-alone GFETs using similar substrates3,4,10,17. This fundamental process compatibility issue apparently hinders the progress of graphene RF research.

Here, we present the rst multi-stage graphene RF IC fabricated in a standard silicon fab. The device integrity is fully preserved and the circuit performance is conrmed by the demonstration of successful receiving and recovering of digital text carried on a GHz signal. The device degradation issue is overcome by completely reversing the conventional fabrication ow, where all passive components together with device gates are rst built on 8-inch silicon wafers before the graphene lms, grown by chemical vapour deposition (CVD) methods18, are transferred. The demonstrated conversion gain at the same local oscillator (LO) input power is B10,000 better than previously reported

graphene IC16. This novel integration scheme can also be applied to any channel materials that can be transferred, such as carbon nanotubes19 or other two-dimensional nanomaterials20,21.

ResultsPassive-rst active-last fabrication ow. Figure 1a shows schematics of the simplied fabrication ow, which depicts the establishment of the passive-rst active-last integration scheme. Inductors and bottom plate of capacitors were rst fabricated at M1 metal level using single Cu damascene process. To get

high-quality factor (Q) of the inductors, M1 was thicker than 1 mm, and can be the same top metal level in standard Si complementary metaloxidesemiconductor (CMOS) chips for global power distribution. The fabricated inductors showed inductances matching the designed values (Supplementary Table 1) with Q48 (Supplementary Fig. 1). The M2 metal level formed by the similar Cu damascene process served as the top plate of capacitors as well as the bottom (wide) part of the embedded T-shaped gate. The M3 metal lines were then patterned to form the top part of the T-shaped gate, where the width of M3 lines dened the transistors channel length. After the T-gate formation, atomic layer deposition (ALD) was used to deposit gate dielectric of 10 nm Al2O3 followed by CVD graphene transfer and patterning. The mobility of the CVD graphene is around 2,0002,500 cm2 (Vs) 1 at the carrier density of 2 1012 cm 2 (Supplementary Fig. 2).

No seed layers that are typically needed for promoting the nucleation of gate dielectric on graphene were required, resulting in high gate dielectric quality and the potential for future scaling.

Graphene

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Si (CMOS devices)

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Figure 1 | Fabrication and architecture of graphene receiver IC.(a) Schematic of the passive-rst active-last process ow showing how the IC fabrication can be integrated into standard Si BEOL process. Four metal levels (M1M4) are required to complete the circuit. (b) Tilted view scanning electron microscopic (SEM) image revealing the integration of key components in IC with enlarged view showing the advanced gate structure of the graphene eld-effect transistors (GFET). Inset image shows cross-sectional SEM of embedded T-shaped gate. Scale bar, 500 nm.

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As the last step, the M4 metal level comprising Pd/Au stack was deposited to form resistors and also device source/drain contacts.

To illustrate the integration architecture, a tilted view scanning electron microscopic image capturing key circuit components from the wafer completing the gate fabrication, before graphene transfer, is shown in Fig. 1b. All the inter-metal dielectrics as well as gate dielectric were stripped off to reveal the underlying structure. The unique embedded T-shaped gate structure in Fig. 1b, together with the multiple-nger design, provides very low gate resistance while maintaining a short channel length, leading to notably improved fMAX veried from stand-alone RF transistors built on the same chip (Supplementary Fig. 3)22.

The IC consists of 11 components including 3 GFETs, 4 inductors, 2 capacitors and 2 resistors (Fig. 2a,b). The circuit is designed as an RF receiver front-end comprising three stages. Each stage is connected to the next through capacitive coupling; thus, the gate bias (Vg) of each stage can be individually adjusted to optimize circuit performance. The rst two stages are designed

as band-pass ampliers, providing amplication and ltering of received RF signal. The third stage performs mixing with LO signal that down-converts the GHz RF signal to much lower intermediate frequency (IF) in the MHz range. Although the ambipolar nature of graphene enables several new circuit designs12,23, including subharmonic mixer operation14, these mixers require the Dirac point close to zero gate bias with highly symmetric electron and hole transfer curves for the best performance, and relatively high levels of LO power. In our design, a fundamental drain-pumped mixer is employed since it leads to better performance based on the characteristics of our graphene transistors (shown in Fig. 2dg), and results in low LO power requirements (o0 dBm). Inductor L4, connected at the drain of mixing FET, serves a double purpose: it resonates the drain capacitance of transistor T3 to provide a large LO voltage swing at the drain terminal, and it attenuates the LO signal leakage towards the IF port. The photo of a fabricated chip in Fig. 2c exhibits arrays of graphene ICs, transistors for

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Figure 2 | Circuit diagram and device DC performance. (a) Circuit schematic of three-stage graphene receiver IC comprising 11 active and passive components. (b) Optical micrograph of an IC under testing. The circuit has the dimension of 1,020 600 mm2. Scale bar, 100 mm. (c) Photo of a fully

processed graphene IC chip. (d) Drain currents as a function of gate biases for three transistors in one circuit and (e) their width normalized transconductances. The drain biases were 1 V. (f) Drain currents as a function of drain biases and (g) width normalized output conductances from the

same devices. The gate biases were 0.25 V for both devices T1 and T2, and 0.75 V for device T3.

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S-parameter characterization and process monitor structures (Supplementary Fig. 4).

One key feature of this process ow is to fabricate GFET as the last step, which prevents possible graphene damage during harsh BEOL processes (for example, chemical mechanical polishing and Cu electroplating). This advantage can be clearly seen from direct current performance of three GFETs of gate lengths of 900 nm and device widths of 12 mm in one circuit measured after the full circuit has been built, as shown in Fig. 2, where Fig. 2d,e and Fig. 2f,g present transfer and output characteristics, respectively. At 1 V drain bias (Vd), these devices exhibit peak transcon

ductance (gm) larger than 0.3 mS mm 1, on par with state-of-theart GFETs with similar device dimensions and about 450% better than the device in the previous graphene IC report despite a higher Vd (1.6 V) was used16. More importantly, the devices show clear drain current saturation (veried by low output conductance (gds) in Fig. 2g), leading to high intrinsic gain (gm gds 1) of about 24.5. We would like to point out that the gapless band structure in graphene typically causes the weaker saturation of the drain current in GFET compared with other semiconductor devices with a bandgap24. We have previously shown that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation (gds 0) can be achieved in GFETs25. Therefore, a higher gain

performance can be expected by continuously improving the gate dielectric quality in our IC fabrication process. At 1 V drain bias, fT and fMAX ranging from 8 to 10 GHz and from 8.5 to 13.5 GHz, respectively, were measured from stand-alone RF transistors with the same gate length. It is noteworthy that the current chips have not gone through the last passivation step. Several reports have shown that various dielectric lms can be directly deposited on graphene, such as Si3N4 deposited by plasma-enhanced CVD26 or a NO2 and HfO2 stack deposited by ALD27, which can provide sufcient chip protection.

IC performance. Before testing the IC as an RF receiver, the successful circuit integration was veried by measuring it as an RF amplier driving a 50-O load, a standard impedance in RF systems. A small-signal power gain of 10 dB at 1 GHz has been previously demonstrated with a discrete graphene transistor28. This circuit function in our IC can be achieved by simply adjusting gate biases of transistors to their highest gm points, and replacing the IF output in Fig. 2a with the third-stage drain bias. Figure 3a shows that the IC exhibits 4 dB power gain, which is

the rst graphene IC able to perform amplication when loaded with 50 O impedance. This performance is in good agreement with circuit simulations performed using the measured values of individual components (Supplementary Fig. 5, Supplementary Note 1). To demonstrate that each of the three active stages is operational, Fig. 3bd shows the normalized gain as a function of Vg in one stage while keeping Vg of other two stages constant. The gain of each stage can be independently controlled, conrming the correct functions from all active and passive components in each stage. In addition, the stability of the graphene IC was tested by applying high drain current stress and monitoring the gain variation continuously (Fig. 3e). The initial performance improvement is attributed to the current-induced annealing effect that removes contamination of graphene29. Once transistors become stabilized, the circuit exhibits less than 1 dB variation during 420 h testing period, suggesting excellent stability and reliability.

The circuit was measured in receiver mode, with an LO signal applied at the drain of T3 and IF output measured after L4. The measured output spectrum is shown in Fig. 4a. The conversion gain of the circuit with 4.3 GHz RF input signal is 10 dB

with a low LO input power (PLO) of 2 dBm, presenting 50

times higher conversion gain with 200 times smaller LO power compared with previously reported graphene IC (Supplementary Table 2)16. Such low PLO is important to effectively prevent LO

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at 4.8 GHz. (b) Normalized amplier output power as a function of the rst-stage gate bias (Vg,1). The second-stage gate bias (Vg,2) was kept at

0.13 V and the third-stage gate bias (Vg,3) was kept at 0.99 V. (c) Normalized amplier output power as a function of Vg,2. Vg,1 0.45 V and Vg,3 0.99 V.

(d) Normalized amplier output power as a function of Vg,3. Vg,1 0.45 V and Vg,2 0.13 V. (e) Variation of amplier gain during bias stress test

for over 22 h. The circuit was measured in air.

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NATURE COMMUNICATIONS | DOI: 10.1038/ncomms4086 ARTICLE

from leaking into the nal IF output. The measured conversion

gain as a function of PLO is also shown in Supplementary Fig. 6.

With drain biases of 1.5 V, the whole three-stage IC consumes

less than 20 mW power, 600% lower than single-stage graphene IC in ref. 16. Figure 4b shows the measured receiver output tones (P1F, P2F, P3F) as a function of input RF power (PRF); low RF harmonic distortion (P1FP2FB30 dB for PRF 0 dBm) indicates

good circuit linearity. The circuit is designed to band-pass lter the RF input signal before entering the mixer to improve the data quality by rejecting unwanted signals outside the carrier frequency band. The effective RF input ltering can be seen from the sharp frequency response in Fig. 4c (B1 GHz of 3-dB bandwidth). The receiver conversion gain is also measured as a function of the LO frequency (Fig. 4d).

To best demonstrate the true functionality of the graphene IC, an RF carrier of 4.3 GHz was amplitude modulated with a bit stream and sent into the receiver to mimic the typical digital data transmitted via wireless carrier. Measured single bit waveforms in Fig. 4e show undistorted IF output signal from the receiver

without the aid of any additional signal amplication, suggesting that a high-quality receiver function has been achieved. The original binary code can then be easily recovered by rectication and low-pass ltering. Figure 4f further shows that bit stream comprising ASCII code of IBM modulated at 20 Mb s 1 is successfully received and demodulated. The modulation rate is limited by the test equipment, and not by the receiver IC.

DiscussionThe demonstration of multifunctional RF ICs built with the graphene-last ow in Si fab clearly paves the way for seamless heterogenous three-dimensional (3D) system integration, where graphene ICs BEOL can be co-integrated with standard Si CMOS BEOL as illustrated in Fig. 1a. On the other hand, stacking conventional semiconductor layers such as Si or III-V into 3D system is rather complicated and costly, where challenges arise from high-temperature annealing processes (typically41,000 C)

required for each active layer device formation that are not

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Figure 4 | Graphene IC measured as RF receiver. (a) Output spectrum of graphene receiver with 900 nm gate length. RF input signal was 20 dBm at

4.3 GHz and LO input signal was 2 dBm at 4.2 GHz. Down converted IF output signal at 100 MHz (fIF fRF fLO) was 30 dBm. (b) Normalized

output power of the fundamental tone (P1F), the second harmonic (P2F) and the third harmonic (P3F) as a function of RF power (PRF), showing no gain compression up to 10 dBm PRF. (c) Normalized output power as a function of LO frequency. (d) Normalized output power as a function of RF.

(e) Measured waveforms of RF input signal amplitude modulated at a rate of 20 Mb s 1, IF output signal and restored binary code after rectifying and low-pass ltering IF signal. (f) A screenshot of receiver output waveforms taken from the oscilloscope, with LO power of 2 dBm at 4.2 GHz. The

original bit stream comprising three letters (24 bits) was recovered by graphene receiver with very low distortion. The circuit was measured in air.

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compatible to Cu BEOL technology30. Our entire IC fabrication ow does not require any process steps higher than 400 C, making it an ideal candidate for monolithic 3D integration with Si CMOS backbone. Such integration concept fully utilizes the transfer property of graphene, and one can envision that high-performance graphene RF circuits will be directly built on top of high-density Si CMOS logic circuits to form an extremely low-cost, ultra-compact communication system.

Methods

CVD graphene growth and transfer. The graphene growth was carried out in a 4-inch furnace, which can support up to 12 12 inch2 graphene size. A Cu foil

(99.99% from Kamis) was annealed at 1,050 C for 5 min in 5 mTorr CH4 for initial graphane island growth, and then annealed for 20 min in 75 mTorr CH4 for graphene growth18. The graphene was transferred to a target substrate with typical wet transfer process. First, 150 nm thick PMMA was spin coated on the graphene/ Cu foil sample (3,000 r.p.m. for 1 min). The polymethyl methacrylate (PMMA)/ graphene/Cu foil sample was then oated on 1 M FeCl3 to dissolve the Cu foil, followed by moving the remaining PMMA/graphene sample on 1 M HCl for rinsing away the residue of Cu etchant. Finally, the PMMA/graphene sample was scooped by a target substrate and then blown dry by pure nitrogen.

Passive-rst active-last process ow. A total of nine lithography masks are required to complete the IC fabrication. In a 200-mm silicon fab, beginning with low-doped Si wafers with 2 mm thick silane oxide deposition at 400 C, the wafer was then spin coated with photoresist and patterned using an ASML Deep ultra-violet stepper. High-power reactive ion etching (RIE) with a mixture of C4F8 and

Ar for 135 s was used to remove E1 mm SiO2, and the photoresist was stripped off in oxygen plasma. Physical vapour deposited liner consisting of TaN/Ta was adapted before the deposition of a thin Cu seed layer, which was followed by Cu electroplating and chemical mechanical polishing. After inspection of post-CMP patterns, low-stress CVD nitride (100 nm) and silane oxide (800 nm) were deposited. The measured capacitance of plate capacitors is 6.1 103 pF cm 2. Cu

vias and following metal levels were fabricated using similar process steps with different dielectric thickness and etch time. Al2O3 gate dielectric (100 ) was then deposited at 250 C using TMA and H2O in a Fiji ALD system to cover the whole wafer and an HBr-based RIE process was used to etch open the contact pad to the gate. After CVD-grown graphene was transferred, photoresist was again patterned in a DUV system and the exposed graphene area was etched away in a Unaxis RIE system with a 50-W plasma maintained by 30 s.c.c.m. O2. Photolithographic patterning was used to dene source/drain electrodes and electron beam evaporation was used to sequentially deposit 0.2 nm Ti, 20 nm Pd and 30 nm Au followed by a lift-off process in resist stripper.

IC measurement. The LO signal was provided by a Wiltron 69047A signal generator, and the input RF signal was provided by a Rohde & Schwarz SMIQ06B signal generator, which could be 100% amplitude modulated to about 20 MHz by an external signal. The mixer and amplier outputs were measured with an Agilent E4448A spectrum analyser. Losses due to bias tees, cables and probe resistance were calibrated using an on-wafer through wire structure. Modulation of the input RF signal was performed by driving the RF signal generator amplitude modulation input with a data pattern stored on an Agilent 81133 pulse generator. The demodulated signal was observed on an Agilent DSA91204A real-time oscilloscope, which also performed the rectication and low-pass ltering to convert it to digital format.

References

1. Cheng, R. et al. High frequency self-aligned graphene transistors with transferred gate stack. Proc. Natl Acad. Sci. 109, 1158811592 (2012).

2. Koswatta, S. O., Valdes-Garcia, A., Steiner, M. B., Lin, Y. M. & Avouris, P. Ultimate RF performance potential of carbon electronics. IEEE Trans. Microw. Theory Tech. 59, 27392750 (2011).

3. Dimitrakopoulos, C. et al. Wafer-scale epitaxial graphene growth on the Si-face of hexagonal SiC (0001) for high frequency transistors. J. Vac. Sci. Technol. B 28, 985992 (2010).

4. Lin, Y.-M. et al. 100-GHz transistors from wafer-scale epitaxial graphene. Science 327, 662 (2010).

5. Kim, S. et al. Realization of a high mobility dual-gated graphene eld-effect transistor with Al2O3 dielectric. Appl. Phys. Lett. 94, 062107 (2009).

6. Meric, I. et al. High-frequency performance of graphene eld effect transistors with saturating IV-characteristics. IEEE Int. Electron Devices Meet. 2.1.12.1.4 (2011).

7. Madan, H. et al. Record high conversion gain ambipolar graphene mixer at10 GHz using scaled gate oxide. IEEE Int. Electron Devices Meet. 4.3.14.3.4 (2012).

8. Guo, Z. et al. Record maximum oscillation frequency in C-Face epitaxial graphene transistors. Nano Lett. 13, 942947 (2013).

9. Liao, L. et al. High speed graphene transistors with a self-aligned nanowire gate. Nature 467, 305308 (2010).

10. Wu, Y. Q. et al. State-of-the-art graphene high-frequency electronics. Nano Lett. 12, 30623067 (2012).

11. Han, S.-J. et al. High-frequency graphene voltage amplier. Nano Lett. 9, 36903693 (2011).

12. Wang, H., Hsu, A. L. & Palacioset, T. Graphene electronics for RF applications. IEEE Microw. Mag. 13, 114125 (2012).

13. Ramn, M. E. et al. 3 GHz graphene frequency doubler on quartz operating beyond the transit frequency. IEEE Trans. Nanotech. 11, 877883 (2012).

14. Habibpour, O., Cherednichenko, S., Vukusic, J., Yhland, K. & Stake, J. A subharmonic graphene FET mixer. IEEE Electron. Dev. Lett. 33, 7173 (2012).

15. Habibpour, O., Vukusic, J. & Stake, J. A 30-GHz integrated subharmonic mixer based on a multichannel graphene FET. IEEE Trans. Microw. Theory Tech. 61, 841847 (2013).

16. Lin, Y.-M. et al. Wafer-scale graphene integrated circuit. Science 332, 12941297 (2011).

17. Moon, J. S. et al. Top-gated epitaxial graphene FETs on Si-face SiC wafers with a peak transconductance of 600 mS/mm. IEEE Electron. Dev. Lett. 31, 260262 (2010).

18. Li, X. et al. Graphene lms with large domain size by a two-step chemical vapor deposition process. Nano Lett. 10, 43284334 (2010).

19. Cao, Q. et al. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nat. Nanotechnol. 8, 180186 (2013).

20. Hsu, A. et al. Large-area 2-D electronics: Materials, technology, and devices. Proc. IEEE 99, 115 (2013).

21. Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147150 (2011).

22. Han, S.-J., Oida, S., Jenkins, K. A., Lu, D. & Zhu, Y. Multinger embedded T-shaped gate graphene RF transistors with high fMAX/fT ratio. IEEE Electron.

Dev. Lett. 34, 13401342 (2013).23. Yang, X., Lir, G., Balandin, A. A. & Mohanram, K. Triple-mode single-transistor graphene amplier and its applications. ACS Nano 4, 55325538 (2010).

24. Schwierz, F. Graphene transistors: status, prospects, and problems. Proc. IEEE 101, 15671584 (2013).

25. Han, S.-J., Reddy, D., Carpenter, G. D., Franklin, A. D. & Jenkins, K. A. Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and theory. ACS Nano 6, 52205226 (2012).

26. Zhu, W. J., Neumayer, D., Perebeinos, V. & Avouris, P. Silicon nitride gate dielectrics and band gap engineering in graphene layers. Nano Lett. 10, 35723576 (2010).

27. Farmer, D. B., Valdes-Garcia, A., Dimitrakopoulos, C. & Avouriset, P. Impact of gate resistance in graphene radio frequency transistors. Appl. Phys. Lett. 101, 143503 (2012).

28. Andersson, M. A., Habibpour, O., Vukusic, J. & Stake, J. 10 dB small-signal grapheme FET amplier. Electron. Lett. 48, 861863 (2012).

29. Moser, J., Barreiro, A. & Bachtold, A. Current-induced cleaning of graphene. Appl. Phys. Lett. 91, 163513 (2007).

30. Emma, P. G. & Kursun, E. Is 3D chip technology the next growth engine for performance improvement? IBM J. Res. Develop. 52, 541552 (2008).

Acknowledgements

We thank James Bucchignano, Simon Dawes and staffs of IBM Microelectronics research Laboratory for their technical assistance. This work was supported in part by the DARPA Open Manufacturing Program (Contract number HR0011-120C-0038).

Author contributions

S.-J.H. conceived and designed the experiments; A.V.G. and S.-J.H. designed the circuit;S.-J.H. developed the integration process and fabricated the circuit; S.O. synthesized CVD graphene; S.-J.H., A.V.G. and K.A.J. performed the device and circuit measurement and analysed the data; S.-J.H. wrote the manuscript. All authors discussed the results and commented on the manuscript.

Additional information

Supplementary Information accompanies this paper at http://www.nature.com/naturecommunications

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How to cite this article: Han, S.-J. et al. Graphene radio frequency receiver integrated circuit. Nat. Commun. 5:3086 doi: 10.1038/ncomms4086 (2014).

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Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6mm(2) area and fabricated on 200mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

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Graphene radio frequency receiver integrated circuit

Author

Han, Shu-jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

Pages

3086

Publication year

2014

Publication date

Jan 2014

Publisher

Nature Publishing Group

e-ISSN

20411723

Source type

Scholarly Journal

Language of publication

English

DOI

https://doi.org/10.1038/ncomms4086

ProQuest document ID

1492527830

Graphene radio frequency receiver integrated circuit

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