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Copyright © 2015 Xiao Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8 μW. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30 μm × 30 μm, resulting in that the integration capacitor should be selected as 0.74 pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1 μV. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix.

Details

Title
A Modularized Noise Analysis Method with Its Application in Readout Circuit Design
Author
Wang, Xiao; Zelin Shi; Xu, Baoshu
Publication year
2015
Publication date
2015
Publisher
Hindawi Limited
ISSN
1065514X
e-ISSN
15635171
Source type
Scholarly Journal
Language of publication
English
ProQuest document ID
1713904516
Copyright
Copyright © 2015 Xiao Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.