Diamond Based Field-Effect Transistors of Zr Gate with SiNx Dielectric Layers

Abstract

Investigation of Zr-gate diamond field-effect transistor with [subscript]SiNx[/subscript] dielectric layers (SD-FET) has been carried out. SD-FET works in normally on depletion mode with p-type channel, whose sheet carrier density and hole mobility are evaluated to be 2.17 × 1013 cm-2 and 24.4 cm2·V-1·s-1, respectively. The output and transfer properties indicate the preservation of conduction channel because of the [subscript]SiNx[/subscript] dielectric layer, which may be explained by the interface bond of C-N. High voltage up to -200 V is applied to the device, and no breakdown is observed. For comparison, another traditional surface channel FET (SC-FET) is also fabricated.

Academic Editor:Jose Alvarez

Key Laboratory for Physical Electronics and Devices of the Ministry of Education, Xi'an Jiaotong University, Shaanxi, Xi'an 710049, China

Received 24 March 2015; Accepted 23 April 2015; 25 October 2015

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1. Introduction

Diamond appears promising for high-power and high-frequency devices, since it has remarkable properties, such as wide band gap ( [figure omitted; refer to PDF] ) of 5.47 eV, the highest thermal conductivity (22 W/cm [figure omitted; refer to PDF] K), high breakdown field (10 MV/cm), high carrier mobility of electron 4500 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 , hole 3800 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 , and high carrier velocity (10⁷ cm/s) [1-4]. However, due to the large activation energies of dopants (boron, phosphorus, and nitrogen) for diamond at room temperature, carrier concentrations in the diamond are very low [1, 5], which limit the development of the diamond-based semiconductor devices. Recently, most FETs based on diamond focus on the hydrogen-terminated surface [6-9], which can introduce a p-type conduction layer with a sheet hole density and hole mobility of 10¹³ cm^-2 and 50-150 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 [10, 11], respectively. In this case, a two-dimensional hole gas (2DHG) exists near the surface of the diamond, associated with the electrochemical potential of adsorbates on a humidity saturated surface [12]. Thus, the conduction surface is thermally and chemically instable and vulnerable to the ambient environment. The oxidation of diamond surface or higher annealing even in vacuum could lead to the missing of 2DHG and degrade the performance of FET device.

This problem can be solved by applying dielectric layers to the diamond surface to maintain the conduction channel for stabilizing or replacing the adsorbates. Various dielectric layers of the H-terminated diamond surface, such as SiO₂ [13], Al₂ O₃ [14], AlN [15], HfO₂ [16], LaAlO₃ [17], Ta₂ O₅ [18], and ZrO₂ [19], have been mainly used as the insulators by the method of thermal evaporation, atomic layer deposition (ALD), or metal organic chemical vapor deposition (MOCVD). However, there are few reports on using dielectric of [figure omitted; refer to PDF] .

In this paper, the single crystal diamond FET with [figure omitted; refer to PDF] layers was proposed, and its properties were studied. For comparison, traditional H-termination surface channel FET was also fabricated.

2. Device Fabrication

Undoped homoepitaxial diamond films were grown on high-temperature high-pressure (HTHP) synthesized (001) IIa single crystal diamond substrates with the dimension of 3 × 3 × 0.5 mm³ by a microwave plasma CVD system (AX5200S Seki Technotron Corp.). Before growth, the substrates were dipped into a mixed acid of HNO₃ and H₂ SO₄ (1 : 1) at 250°C for 1 hour to remove nondiamond phase. During growth, the total flow rate of the reaction gas was 500 sccm, and the ratio of CH₄ /H₂ was 1%. The process pressure, growth temperature, and microwave power were 100 Torr, 900°C, and 1 kW, respectively. After growth, the samples were kept in hydrogen plasma for 1 minute at 900°C to generate a hydrogen-terminated surface.

The fabrication began with a standard lithography to pattern the drain and source electrodes before the metal evaporation. A carbon soluble metal palladium (Pd) was selected as the electrodes because of its good adhesion and relatively low specific contact resistance with the diamond surface [20]. Next, mesa isolation, protected by the photoresist, was performed on the grown diamond film by irradiation of O₃ and UV rays for 15 mins. The [figure omitted; refer to PDF] dielectric layer was then deposited onto the surface at the temperature of 250°C and etched using BOE (6 : 1) solution for the patterns. Some of the device's channels were not covered with [figure omitted; refer to PDF] for comparison. Zirconium (Zr) as the gate metal was finally sputtered onto the channels. The total fabrication process procedure is shown in Figure 1. The gate length ( [figure omitted; refer to PDF] ) and width ( [figure omitted; refer to PDF] ) for both of the devices were 3 µ m and 90 µ m, respectively. The electrical properties of the device with and without [figure omitted; refer to PDF] layers were then investigated.

Figure 1: The process flow of the device fabrication.

[figure omitted; refer to PDF]

3. Results and Discussion

The optical microscope and AFM images of as-deposited single crystal diamond epitaxial films are shown in Figure 2. Figure 2(a) presents the full-scale of the growth film with the dimension of 3 × 3 mm² ; no point defect pits and steps are found in the surface, indicating remarkable quality for electronic device fabrication. Figure 2(b) displays the AFM image in the area of 5 × 5 µ m² . The root mean square (RMS) roughness was measured to be 0.446 nm, illustrating an adequate morphology for device fabrication.

Figure 2: The optical microscope image (5x) (a) and AFM photo of MPCVD deposited single crystal diamond epitaxial films.

[figure omitted; refer to PDF]

The room temperature properties of the Zr-gate diamond based field-effect transistors were investigated. The output characteristics are exhibited in Figure 3, where the drain current ( [figure omitted; refer to PDF] ) has been normalized with respect to [figure omitted; refer to PDF] . The blue solid line and the red dash dotted line indicate the FETs with and without [figure omitted; refer to PDF] gate dielectric, respectively. As can be seen in Figure 3, the absolute value of [figure omitted; refer to PDF] ( [figure omitted; refer to PDF] ) for SD-FET increases with an increasing absolute value of [figure omitted; refer to PDF] ( [figure omitted; refer to PDF] ), confirming that the channel under [figure omitted; refer to PDF] is p-type with hole-carriers. It is the evidence that the channel at the [figure omitted; refer to PDF] /diamond interface is preserved, which may be related to the C-N bonds [21]. In addition, the device operates in the normally on depletion mode. An obvious typical output characteristic for both of the FETs could be found in the figure. As the [figure omitted; refer to PDF] increases, [figure omitted; refer to PDF] increases linearly in the linear region, and the drain current ( [figure omitted; refer to PDF] ) becomes saturated in the saturation region. Compared with the output characteristic of the SC-FET, the [figure omitted; refer to PDF] of SD-FET is larger when [figure omitted; refer to PDF] V and gets close at [figure omitted; refer to PDF] V. And the max current density is consistent for both kinds of devices. This interesting phenomenon may be in connection with the interface states where the charges are trapped.

Figure 3: FET output characteristics of the Zr-gate diamond based field-effect transistors with and without [figure omitted; refer to PDF] dielectric layers.

[figure omitted; refer to PDF]

As shown in Figure 4, the transfer and transconductance curves of the two kinds of devices are familiar. Based on the [figure omitted; refer to PDF] - [figure omitted; refer to PDF] relationship, the threshold voltage is determined to be 0.75 V for SD-FET and 0.65 V for SC-FET. The transconductance characteristics presented in Figure 4 were measured at [figure omitted; refer to PDF] V. The maximum [figure omitted; refer to PDF] is 1.19 mS/mm at [figure omitted; refer to PDF] to -3.5 V and 1.22 mS/mm at [figure omitted; refer to PDF] to -5 V for SC-FET and SD-FET, respectively.

Figure 4: The transfer and transconductance of the devices with and without [figure omitted; refer to PDF] layer.

[figure omitted; refer to PDF]

The charge carrier profile can be derived from the room temperature capacitance-voltage (CV) measurements. Figure 5 shows the calculated profile of H-terminated diamond surface as a function of the depth from the metal/diamond interface. The 2DHG is clearly identified to be 6.6 nm underneath the surface of diamond, corresponding to a gate-to-channel capacitance of 0.76 μ F/cm² . The sheet charge density was calculated to be 2.03 × 10¹³ cm^-2 according to the integration of the profile as revealed in Figure 5. Using the sheet resistance of 11.0 kΩ measured by TLM method, the hole mobility was derived to be 28.0 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 .

Figure 5: Hole-density depth profile in diamond from the H-terminated diamond according to the CGS-VG curve.

[figure omitted; refer to PDF]

Figure 6 exhibits the charge carrier profile of SD-FET with a lower gate-to-channel capacitance of 0.17 μ F/cm² , because of the series connection of the intrinsic gate capacitor and the [figure omitted; refer to PDF] gate dielectric capacitor. The permittivity of [figure omitted; refer to PDF] ( [figure omitted; refer to PDF] ) and diamond for dielectric layer and gate capacitor were used to evaluate the depth profile. The 2DHG was determined to be 26.2 nm under the interface of [figure omitted; refer to PDF] /diamond. As the 2DHG of H-terminated diamond located 6.6 nm under the surface, the thickness of [figure omitted; refer to PDF] was estimated to be 19.6 nm, in accordance with nominal thickness of 20 nm. Integration of the charge carrier profile yields a sheet charge concentration of [figure omitted; refer to PDF] cm^-2 . Based on sheet resistance of 11.8 kΩ and the carrier density, the mobility was extracted to be 24.4 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 , indicating that it is consistent with that of SC-FET.

Figure 6: Hole-density depth profile in diamond from the [figure omitted; refer to PDF] /diamond interface according to the CGS-VG curve.

[figure omitted; refer to PDF]

The plot of the drain current versus the drain-source voltage up to -200 V is investigated in Figure 7. For SD-FET (Figure 7(a)), [figure omitted; refer to PDF] increases quickly with the voltage increases from 0 V to 50 V and then starts to saturate until the applied voltage gets to -200 V. The max [figure omitted; refer to PDF] was measured to be about 8 μ A. However, the device does not break down through drain and source; the output and transfer properties are the same as those before applying such high voltage. The relative high drain current may come from the leakage path, which could be related with the defects center at the interface of [figure omitted; refer to PDF] and diamond. The defect centers are something like impurity charges. As the voltage begins to apply, the charges start to move along the direction of the voltage, and the current also increases. When the voltage reaches -50 V, all the charges get involved in the moving, so the current gets saturated. It is worth noting that these charges are out of the control of the gate voltage. The [figure omitted; refer to PDF] of SC-FET (Figure 7(b)) increases slightly with the voltage and gets to 10 nA at -200 V, a very low drain-source leakage, showing a strong control of the Zr-gate metal.

Figure 7: High voltage of [figure omitted; refer to PDF] applied on (a) SC-FET and (b) SD-FET at [figure omitted; refer to PDF] V.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

4. Conclusion

In this work, SD-FET has been demonstrated with a 20 nm thick [figure omitted; refer to PDF] dielectric layer on (001) oriented H-termination diamond film. For comparison, a standard SC-FET was also fabricated. The transistor output and transfer characteristics of both devices were observed, confirming the presence of the 2DHG at the surface and the interface, respectively. Notably, the maximum drain current of SD-FET was the same compared with SC-FET. The modulated 2DHG sheet charge densities extracted from CV curves were 2.03 × 10¹³ cm^-2 and 2.17 × 10¹³ cm^-2 for SC-FET and SD-FET, respectively. The hole mobility was calculated to be 28 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 and 24.4 cm² [figure omitted; refer to PDF] V^-1 [figure omitted; refer to PDF] s^-1 for SC-FET and SD-FET, respectively. The cut-off drain current was measured, and no breakdown was presented as the drain-source voltage was applied as high as -200 V. The results indicated that the channels had been preserved after [figure omitted; refer to PDF] deposition. The preserving channel may be related to C-N formation at the [figure omitted; refer to PDF] /diamond interface.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

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