Full Text

Turn on search term navigation

Copyright © 2018 Li Luo et al. This is an open access article distributed under the Creative Commons Attribution License (the “License”), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License. https://creativecommons.org/licenses/by/4.0/

Abstract

CPU has insufficient resources to satisfy the efficient computation of the convolution neural network (CNN), especially for embedded applications. Therefore, heterogeneous computing platforms are widely used to accelerate CNN tasks, such as GPU, FPGA, and ASIC. Among these, FPGA can accelerate the computation by mapping the algorithm to the parallel hardware instead of CPU, which cannot fully exploit the parallelism. By fully using the parallelism of the neural network’s structure, FPGA can reduce the computing costs and increase the computing speed. However, the development of FPGA requires great design skills. As a heterogeneous development platform, OpenCL has some advantages such as high abstraction level, short development cycle, and strong portability, which can make up for the lack of skilled designers. This paper uses Xilinx SDAccel to realize the parallel acceleration of CNN task, and it also proposes an optimizing strategy of single convolutional layer to accelerate CNN. Simulation results show that the calculation speed could be improved by adopting the proposed optimizing strategy. Compared with the baseline design, the strategy of single convolutional layer could increase the computing speed 14 times. Performance of the whole CNN task could be improved 2 times more than before, and the speed of image classification could attain more than 48 fps.

Details

Title
Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL
Author
Luo, Li 1 ; Wu, Yakun 1 ; Qiao, Fei 2   VIAFID ORCID Logo  ; Yang, Yi 2 ; Qi, Wei 2   VIAFID ORCID Logo  ; Zhou, Xiaobo 1 ; Fan, Yongkai 3   VIAFID ORCID Logo  ; Xu, Shuzheng 2 ; Liu, Xinjun 4   VIAFID ORCID Logo  ; Yang, Huazhong 2 

 Department of Electronic Science and Technology, Beijing Jiaotong University, Beijing, China 
 Department of Electronic Engineering, Tsinghua University, Beijing, China 
 China University of Petroleum, Beijing, China 
 Department of Mechanical Engineering, Tsinghua University, Beijing, China 
Editor
Michael Hübner
Publication year
2018
Publication date
2018
Publisher
John Wiley & Sons, Inc.
ISSN
16877195
e-ISSN
16877209
Source type
Scholarly Journal
Language of publication
English
ProQuest document ID
2070137075
Copyright
Copyright © 2018 Li Luo et al. This is an open access article distributed under the Creative Commons Attribution License (the “License”), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License. https://creativecommons.org/licenses/by/4.0/