A Novel Step-Up Converter with an Ultrahigh Voltage Conversion Ratio

Abstract

[...]in the last few decades, many researchers and engineers have made much effort to explore a novel step-up converter with a high voltage conversion ratio, and many effective topologies have been proposed. [...]all of the above step-up converters possess an abrupt change in voltage across the capacitor, which limits them in practical applications to some extent. [...]like a boost converter, if an ultrahigh output voltage from those converters is required, the duty cycle D must be close to 1.0, and this also cannot generally be achieved because of the limitations of real semiconductors. [...]for acquiring a higher output voltage with the same polarity as the input voltage with the duty cycle D being close to 0.5, which is very easy to implement in practical situations, some new DC-DC converters have been proposed. (5) The proposed step-up converter has no abrupt changes in capacitor voltage and inductor current, so it does not suffer from infinite capacitor current and inductor voltage. [...]the proposed step-up converter with ultrahigh voltage conversion ratio is a good candidate topology for applications of photovoltaic systems and fuel cell systems, and these applications will be investigated in future work.

1. Introduction

As part of a DC switching power supply, the step-up converter is important for transforming low input voltage into the desired high output voltage to satisfy the requirements of practical applications, such as photovoltaic (PV) systems, fuel-cell systems, etc. Step-up converters can be classified into two types: non-isolated and isolated. An isolated step-up converter is generally constructed by inserting a transformer into a non-isolated step-up converter to enlarge the voltage conversion ratio. However, switch voltage overshoot and EMI problems caused by the transformer make the whole system suffer from low efficiency and huge volume [1,2]. Therefore, the non-isolated step-up converter is the focus of many researchers and engineers. It is well known that the traditional boost converter with a voltage conversion ratio of 1/(1 − D), where D is the duty cycle, is a good topology to realize the boost ability because it has a simple structure [3]. Nevertheless, under certain input voltages, if an extremely high output voltage is required, the duty cycle must be close to 1.0, and this cannot generally be achieved because of the limitations of real semiconductors. Accordingly, in the last few decades, many researchers and engineers have made much effort to explore a novel step-up converter with a high voltage conversion ratio, and many effective topologies have been proposed. For example, for realizing a voltage conversion ratio of (1 + D)/(1 − D), which is higher than that of the traditional boost converter, Yang et al. constructed a transformerless step-up converter [4], Gules et al. introduced a modified single-ended primary-inductor converter (Sepic) [5], and Mummadi proposed a fifth-order boost converter [6]. However, that voltage conversion ratio was limited to some extent.

To achieve a voltage conversion ratio which is higher than (1 + D)/(1 − D) within a certain area of D, several step-up converters have been proposed. For example, for obtaining a voltage conversion ratio of (2 − D)/(1 − D), the following converters have been proposed: KY boost converter constructed by combining a KY converter with a traditional synchronously rectified boost converter [7], a step-up converter constructed by combining KY and buck-boost converters [8], and an elementary positive output super-lift Luo converter [9]. For obtaining a voltage conversion ratio of 2/(1 − D), Hwu et al. combined the charge pump concept with the traditional boost converter to construct a fourth-order step-up converter [10], and Al-Saffar et al. integrated the traditional boost converter with a self-lift Sepic converter to introduce a sixth-order step-up converter [11]. Also, Hwu et al. proposed two voltage-boosting converters with a voltage conversion ratios of (3 − D)/(1 − D) and (3 + D)/(1 − D) by using bootstrap capacitors and boost inductors [12]. Chen et al. proposed an interleaved step-up converter with the voltage conversion ratio being 3/(1 − D) [13]. However, all of the above step-up converters possess an abrupt change in voltage across the capacitor, which limits them in practical applications to some extent. Moreover, like a boost converter, if an ultrahigh output voltage from those converters is required, the duty cycle D must be close to 1.0, and this also cannot generally be achieved because of the limitations of real semiconductors.

Therefore, for acquiring a higher output voltage with the same polarity as the input voltage with the duty cycle D being close to 0.5, which is very easy to implement in practical situations, some new DC-DC converters have been proposed. For example, in [14], based on a Sheppard- Taylor converter whose voltage conversion ratio of −D/(1 − 2D) is negative, a modified Sheppard-Taylor converter with a voltage conversion ratio of D/((1 − D)(1 − 2D)) was proposed. Also, by removing some components of the Sheppard-Taylor converter, a simple modified Sheppard-Taylor converter with a voltage conversion ratio of 1/(1 − 2D) was proposed in [15]. However, its voltage conversion ratio of 1/(1 − 2D) was obtained under the unreasonable assumption that the voltages across its two capacitors were equal. In fact, its voltage conversion ratio was related to not only the duty cycle D, but also the load resistor and the switch frequency, so its load regulation is not good enough [16]. In addition, a fourth-order step-up converter with a voltage conversion ratio of (1 − D)/(1 − 2D) was presented in [17] and a pulse-width modulation (PWM) Z-source DC-DC converter with the same voltage conversion ratio was investigated in [18]. However, their voltage conversion ratios were also limited to some extent. In particular, the output voltage of the PWM Z-source DC-DC converter was floating. Hence, exploring new step-up converters with good performance is very important and valuable. In this study, a new step-up converter with an ultrahigh voltage conversion ratio is proposed. In this converter, the output voltage is common-grounded with the input voltage, and its two power switches conduct synchronically. Even if the two input inductors have different values, the proposed step-up converter can still work appropriately. Additionally, there is no abruptly changing on the current through the inductors and the voltage across the capacitors.

This paper is organized as follows. In Section 2, the structure and basic principle of the proposed step-up converter in continuous conduction mode (CCM) is presented in detail. In Section 3, the averaged model and corresponding small-signal model are established and analyzed. Comparisons among existing step-up converters and the proposed step-up converter are presented in Section 4. Some Saber simulations and circuit experiments for confirmation are presented in Section 5. Finally, some concluding remarks and comments are given in Section 6.

2. Novel Topology’s Structure and Its Basic Principle

A circuit schematic of the proposed step-up converter is shown in Figure 1. It consists of two power switches (Q₁ and Q₂), five diodes (D₁, D₂, D₃, D₄, and D₅), three inductors (L₁, L₂, and L₃), two capacitors (C₁ and C₂), and the resistive load R. Two power switches conduct synchronically and are driven by the same PWM signal v_d, with the period being T and duty cycle being d. The currents through the three inductors are denoted by i_L1, i_L2 and i_L3. The voltages across the two capacitors are defined as v_C1 and v₀. Notably, the proposed step-up converter operating in the continuous conduction mode (CCM) is the only concern here, and its possible stages are shown in Figure 2. Based on the relation between inductors L₁ and L₂, there are three cases for the proposed step-up converter, case 1: L₁ = L₂, case 2: L₁ < L₂ and case 3: L₁ > L₂. The principle of the proposed step-up converter under the three cases is discussed in detail in the following subsections.

2.1. Case 1: L₁ = L₂

For this case, the proposed step-up converter has only two operation stages; their equivalent circuits are shown in Figure 2a,b.

2.1.1. Stage 1

Figure 2a shows that two power switches (Q₁ and Q₂) are turned on for the high level of PWM signal v_d, and three of the diodes D₂, D₄ and D₅ do not conduct for the inverse biased voltage, whereas two of the diodes (D₁ and D₃) conduct for the forward biased voltage. That is, the state of power switches and diodes is: (Q₁, Q₂, D₁, D₂, D₃, D₄, D₅≡ON, ON, ON, OFF, ON, OFF, OFF) within NT < t ≤ NT + dT where N is a natural number. Accordingly, the input voltage source supplies the energy to two input inductors (L₁ and L₂) so that both of them are magnetized and their currents increase. Because L₁ = L₂, the currents through these two inductors are equal, that is, i_L1 = i_L2. Capacitor C₁ is in parallel with inductor L₃. Consequently, capacitor C₁ is discharged so that its voltage decreases and inductor L₃ is demagnetized so that its current also decreases. In addition, capacitor C₂ delivers energy to the resistive load R. The associated equations for stage 1 are:

{d_iL1dt=_vin+_vC1L1d_iL2dt=_vin+_vC1L2d_iL3dt=−_vC1L3d_vC1dt=_iL3−_iL1−_iL2C1d_v0dt=−_v0R_C2

2.1.2. Stage 2

Figure 2b shows that two power switches (Q₁ and Q₂) are turned off for the low level of PWM signal v_d. Three diodes (D₂, D₄, and D₅) conduct, and the remaining diodes (D₁ and D₃) do not conduct. That is, the state of power switches and diodes is: (Q₁, Q₂, D₁, D₂, D₃, D₄, D₅≡OFF, OFF, OFF, ON, OFF, ON, ON) within NT + dT < t ≤ NT + T. Hence, inductor L₁ is in series with inductor L₂, leading to i_L1 = i_L2, and together with the input voltage v_in, they supply the energy to inductor L₃ and capacitor C₁. The corresponding equations for stage 2 are:

{d_iL1dt=_vin−_v0L1+_L2d_iL2dt=_vin−_v0L1+_L2d_iL3dt=_v0−_vC1L3d_vC1dt=_iL3C1d_v0dt=_iL1C2−_iL3C2−_v0R_C2

2.2. Case 2: L₁ < L₂

For case 2, besides stage 1 and stage 2, it has stage 3, as shown in Figure 2c, corresponding to (Q₁, Q₂, D₁, D₂, D₃, D₄, D₅≡OFF, OFF, OFF, ON, ON, ON, ON) within NT + dT < t ≤ NT + dT + d₁₁T because diode D₃ is still conducting for i_L1 > i_L2. Its mathematical model is:

{d_iL1dt=_vin−_v0L1d_iL2dt=0d_iL3dt=_v0−_vC1L3d_vC1dt=_iL3C1d_v0dt=_iL1C2−_iL3C2−_v0R_C2

Notably, stage 3 will last until i_L1 = i_L2, leading to the diode D₃ being off and the proposed step-up converter immediately operating in stage 2. Therefore, the sequence of operations of the proposed step-up converter in case 2 is: stage 1 (Figure 2a) during NT < t ≤ NT + dT, stage 3 (Figure 2c) during NT + dT < t ≤ NT + dT + d₁₁T, and stage 2 (Figure 2b) during NT + dT + d₁₁T < t ≤ NT + T.

2.3. Case 3: L₁ > L₂

For case 3, besides stage 1 and stage 2, it has stage 4, as shown in Figure 2d, corresponding to (Q₁, Q₂, D₁, D₂, D₃, D₄, D₅≡OFF, OFF, ON, ON, OFF, ON, ON) during NT + dT < t ≤ NT + dT + d₂₂T because diode D₁ is still conducting for i_L1 < i_L2. Its equations are:

{d_iL1dt=0d_iL2dt=_vin−_v0L2d_iL3dt=_v0−_vC1L3d_vC1dt=_iL3C1d_v0dt=_iL2C2−_iL3C2−_v0R_C2

Please note that stage 4 will end if i_L1=i_L2, which prevents diode D₁ from conducting and the proposed step-up converter will immediately operate in stage 2. Therefore, the sequence of operations of the proposed step-up converter in case 3 is: stage 1 (Figure 2a) during NT < t ≤ NT + dT, stage 4 (Figure 2d) during NT + dT < t ≤ NT + dT + d₂₂T, and stage 2 (Figure 2b) during NT + dT + d₂₂T < t ≤ NT + T.

3. Modeling and Theoretical Analysis

Based on the averaging method in [19], the averaged model for the proposed step-up converter under the three cases are established and analyzed. Firstly, some symbols are defined. x is defined as the variables of the proposed step-up converter, such as i_L1, i_L2, i_L3, v_C1, v₀, d, and v_in. ⟨x⟩, X and x^ are denoted by their averaged, DC and small AC values, respectively. Also, the following items are assumed:

⟨x⟩=X+x^ with x^<<X

3.1. Averaged Model

3.1.1. Case 1: L₁ = L₂

For this case, L₁ = L₂ so that i_L1 = i_L2. From (1) and (2), and using the averaging method in [19], the averaged model of the proposed step-up converter in case 1 can be directly derived as follows:

{d⟨_iL1⟩dt=⟨_vin⟩+⟨_vC1⟩_L1d+⟨_vin⟩−⟨_v0⟩2_L1(1−d)d⟨_iL3⟩dt=−⟨_vC1⟩_L3+⟨_v0⟩(1−d)_L3d⟨_vC1⟩dt=−2⟨_iL1⟩_C1d+⟨_iL3⟩_C1d⟨_v0⟩dt=⟨_iL1⟩_C2(1−d)−⟨_iL3⟩_C2(1−d)−⟨_v0⟩R_C2

3.1.2. Case 2: L₁ < L₂

As described in Section 2, there are three stages of the proposed step-up converter in case 2. The typical time-domain waveforms for the inductor currents i_L1 and i_L2 and the PWM signal v_d are plotted in Figure 3, where I_LN, I_LM, and I_LN1 are the values of i_L1 and i_L2 at t = NT, t = (N + d + d₁₁)T, and t = (N + 1)T, respectively, and I_L1P is the value of i_L1 at t = (N + d + d₁₁)T.

Based on (1), (2), (3), and Figure 3 and using the geometrical technique, the following equations can be derived:

⟨_vin⟩+⟨_vC1⟩_L1dT+⟨_vin⟩−⟨_v0⟩_L1d11T=⟨_vin⟩+⟨_vC1⟩_L2dT

⟨_iL1⟩=_ILN+_IL1P2d+_IL1P+_ILM2_d11+_ILM+_ILN12(1−d−_d11)

⟨_iL2⟩=_ILN+_ILM2d+_{ILM d11}+_ILM+_ILN12(1−d−_d11)

Hence, the expressions for d₁₁ and ⟨i_L2⟩ can be derived as follows:

_d11=(⟨_vin⟩+⟨_vC1⟩)_L1Kd⟨_v0⟩−⟨_vin⟩

⟨_iL2⟩=⟨_iL1⟩−(⟨_vin⟩+⟨_vC1⟩+^{(⟨_vin⟩+⟨_vC1⟩)2} _L1K⟨_v0⟩−⟨_vin⟩)K^d22f

where K = 1/L₁ − 1/L₂. Thereby, the completed averaged model of the proposed step-up converter in case 2 can be obtained by using the averaging method in (1)–(3), and then combining (10) and (11). The result is:

{d⟨_iL1⟩dt=⟨_vin⟩+⟨_vC1⟩_L1+_L22d+⟨_vin⟩−⟨_v0⟩_L1+_L2(1−d)d⟨_iL3⟩dt=−⟨_vC1⟩_L3d+⟨_v0⟩−⟨_vC1⟩_L3(1−d)d⟨_vC1⟩dt=⟨_iL3⟩_C1−2⟨_iL1⟩_C1d+K^d32f_C1(⟨_vin⟩+⟨_vC1⟩−^{(⟨_vin⟩+⟨_vC1⟩)2} _L1K⟨_vin⟩−⟨_v0⟩)d⟨_v0⟩dt=−⟨_v0⟩R_C2+(⟨_iL1⟩_C2−⟨_iL3⟩_C2)(1−d)

3.1.3. Case 3: L₁ > L₂

As indicated in Section 2, for case 3, the proposed step-up converter also has three stages, and its typical domain waveforms are shown in Figure 4, where I_LN, I_LM, and I_LN1 are the values of i_L1 and i_L2 at t = NT, t = (N + d + d₂₂)T and t = (N + 1)T, respectively, and I_L2P is the value of i_L2 at t = (N + d + d₂₂)T. Because case 3 is similar to case 2, the completed averaged model of the proposed step-up converter for case 3 is directly derived as follows:

{d⟨_iL2⟩dt=⟨_vin⟩+⟨_vC1⟩_L2+_L12d+⟨_vin⟩−⟨_v0⟩_L2+_L1(1−d)d⟨_iL3⟩dt=−⟨_vC1⟩_L3d+⟨_v0⟩−⟨_vC1⟩_L3(1−d)d⟨_vC1⟩dt=⟨_iL3⟩_C1−2⟨_iL2⟩_C1d−K^d32f_C1(⟨_vin⟩+⟨_vC1⟩+^{(⟨_vin⟩+⟨_vC1⟩)2} _L2K⟨_vin⟩−⟨_v0⟩)d⟨_v0⟩dt=−⟨_v0⟩R_C2+(⟨_iL2⟩_C2−⟨_iL3⟩_C2)(1−d)

3.2. DC Equilibrium Point

By substituting (5) into (6), (12), and (13), and then separating DC items, the DC equilibrium points of the proposed step-up converter under three cases can be derived; they are shown in Table 1.

From Table 1, it can be seen that the expressions for the DC voltage V₀ under the three cases are equal. In other words, no matter what the relation between L₁ and L₂ is, the voltage conversion ratio M of the proposed step-up converter can be described as follows:

M=1+D(1−D)(1−2D)

Also, the expressions for the DC voltage V_C1 under three cases are also equal. In conclusion, the relation between L₁ and L₂ does not influence V₀ and V_C1.

3.3. Voltage Stress of Power Switches and Diodes under Three Cases

Based on the definition of the voltage stress on the power switch and diode, the corresponding results for the proposed step-up converter under the three cases can be derived; they are shown in Table 2. One can see that the voltage stresses on the power switches (Q₁ and Q₂) and diodes (D₂, D₄ and D₅) under the three cases are equal except for the diodes D₁ and D₃.

3.4. Ripples for Inductor Currents and Capacitor Voltages

The ripples for the inductor currents and the capacitor voltages can be obtained by using (1) and Table 1. The results are shown in Table 3.

Hence, unlike the voltage ripple for capacitor C₁, the current ripples for inductors (L₁, L₂ and L₃) and the voltage ripples for capacitor C₂ under the three cases are equal. Generally, the ripple ratio, which is defined by the ripple over the corresponding DC value, can be used to select the values of the inductors and capacitors.

3.5. Transfer Functions

The transfer function is fundamental for the consequent controller design for DC-DC converters. By substituting (5) into (6), (12), and (13), and then separating AC items and ignoring the second- and higher-order AC terms because their values are very small, the corresponding transfer functions for the proposed step-up converter under the three cases can be derived by using their respective definitions.

The control-to-output voltage transfer function G_vd(s), the input voltage-to-output voltage transfer function G_vv(s), the control-to-inductor current i_L1 transfer function G_i1d(s), and the input voltage-to-inductor current i_L1 transfer function G_i1v(s) of the proposed step-up converter can be obtained as follows:

_Gvd(s)=_{v^0(s)d^(s)|v^in(s)=0}=[0,0,0,1]^(sI−A)−1 _Bd

_Gvv(s)=_{v^0(s)v^in(s)|d^(s)=0}=[0,0,0,1]^(sI−A)−1 _Bv

_Gi1d(s)=_{i^L1(s)d^(s)|v^in(s)=0}=[1,0,0,0]^(sI−A)−1 _Bd

_Gi1v(s)=_{i^L1(s)v^in(s)|d^(s)=0}=[1,0,0,0]^(sI−A)−1 _Bv

where the expressions for A, B_d and B_v under the three cases are presented in Table 4.

4. Comparisons among Different Topologies

Table 5 shows the comparisons among the modified Sheppard-Taylor converter (MSTC) in [14], the PWM Z-source DC-DC converter (ZSC) in [18], the simple modified Sheppard-Taylor converter (SMSTC) in [15], and the proposed step-up converter (PSUC).

Although the proposed step-up converter has five diodes, while others have less, from Figure 5, which shows the comparisons of the voltage conversion ratio M among these converters under different duty cycle D, it can be seen that the proposed step-up converter possesses the highest voltage conversion ratio. For example, the voltage conversion ratio M of the proposed step-up converter is up to 46.224 at D = 0.47. Additionally, the ZSC’s output voltage is floating, whereas those of the others are not.

5. Saber Simulations and Circuit Experiments

For validation purposes, the circuit for the proposed step-up converter is designed. The given specifications are described as V_in = 12 V, V₀ = 90 V, f = 32 kHz, R = 300 Ω. Thus, from (14), the duty cycle D should be equal to 0.358742. Based on the voltage stresses of the power switches and diodes in Table 2, the HEXFET Power MOSFET IRFP4668 whose V_DSS = 200 V was selected for power switches Q₁ and Q₂, and the Switchmode Schotty Power Rectifier MBR40250 rated for 250 V was selected for diodes D₁, D₂, D₃, D₄, and D₅. Inductors (L₁, L₂ and L₃) can be designed by using their current ripple ratios ε_L = Δi_L/I_L whose values should generally be less than 45%. Capacitors C₁ and C₂ can be designed by using their voltage ripple ratios ε_C = Δv_C/V_C whose values should be less than 20% and 0.5%, respectively. Thereby, from Table 1 and Table 3, the current ripple ratio for each inductor and the voltage ripple ratio for each capacitor under each case can be calculated, and accordingly the selected inductors and capacitors in each case should satisfy conditions: L₁ > 1048 µH, L₂ > 1048 µH, L₃ > 1210 µH, C₁ > 2.06 µF and C₂ > 7.47 µF. Here, C₁ = 4.7 μF with r_C1 = 10 mΩ, C₂ = 40 μF with r_C2 = 6 mΩ, and L₃ = 2.76 mH with r_L3 = 164 mΩ were selected for the proposed step-up converter. Additionally, L₁ = L₂ = 1.2 mH with r_L1 = r_L2 = 70 mΩ were selected for case 1, L₁ = 1.2 mH with r_L1 = 70 mΩ and L₂ = 2.27 mH with r_L2 = 156 mΩ were selected for case 2, and L₁ = 2.27 mH with r_L1 = 156 mΩ and L₂ = 1.2 mH with r_L2 = 70 mΩ were selected for case 3.

From the above-designed circuit parameters, the simulated model in Saber software, which is widely used in the field of power electronics [20], for the proposed step-up converter is constructed, and some measured results on the output voltage V₀ from the saber simulations were presented in Table 6. One can see that the output voltages V₀ for the proposed step-up converter in the three cases were close, and their values were smaller than the required 90 V because the parasitic parameters were considered in the Saber simulations.

Moreover, a hardware circuit for the proposed step-up converter with the same circuit parameters and selected power switches and diodes was also constructed. Notably, in the experiments, the photocoupler TLP250H was applied to drive the power switches. The averaged values of the input voltage V_in, the input current I_in and the output voltage V₀ with different duty cycle D for the proposed step-up converter under case 1 were measured. In addition, then, the voltage conversion ratio M = V₀/V_in and the efficiency η = V₀²/(RV_inI_in) with different duty cycle D for the proposed step-up converter in case 1 were calculated and plotted in Figure 6a,b, respectively. Simultaneously, the corresponding Saber simulations were also detected, calculated, and plotted in Figure 6a,b. It can be seen that the experimental results were in basic agreement with the Saber simulations.

As shown in Table 6, it is necessary to design an appropriate controller for this proposed step-up converter. Based on the circuit parameters, the zeros of G_vd(s) (shown in (15)) can be calculated. The results showed that G_vd(s) was a fourth-order and non-minimum phase since it had right-half side zeros, so that it was difficult to select only the single voltage loop to obtain good performance [21]. Alternatively, an average current mode controller shown in Figure 7 was selected and designed for the proposed step-up converter. This controller had an outer voltage loop and an inner current loop. For the outer voltage loop, it was necessary to detect the output voltage v₀ and design a voltage compensator. For the inner current loop, it was necessary to select one of the inductor currents in the proposed step-up converter and design a current compensator. Due to all the G_i1d(s)’s poles and zeros being in the left-half side of the s-plane, that is, G_i1d(s) is stable and minimum phase, the inductor current i_L1 was selected and measured for the average current mode controller. Notably, the inductor current i_L1 here was transformed into a voltage with the same value through the current transducer LA55-A. The current compensator’s output voltage is denoted by v_vi. AM1 and AM2 were realized by the operational amplifiers LF356 and COM was realized by the voltage comparator LM311. The corresponding parameters were: R_vi = 1000 kΩ, R_vd =20 kΩ, R_vf = 200 kΩ, C_vf = 10 nF, R_i = 20 kΩ, R_p = 180 kΩ, C_p = 10 nF, C_i = 100 pF, V_ref = 1.76 V. The PWM signal v_d was generated by comparing the voltage v_vi with the ramp signal V_ramp, whose expression was given as follows:

_Vramp=_VL+(_VU−_VL)(tTmod1)

where V_L = 0 V, V_U = 10 V and T = 1/f.

The experimental results for the output voltage v₀, the inductor currents i_L1 and i_L2, and the PWM signal v_d for the average-current mode controlled proposed step-up converter under the three cases are presented in Figure 8a–c, respectively. One can see that the output voltages v₀ for the systems under the three cases are really the same, despite different relations between the inductors L₁ and L₂. Moreover, the response of the output voltage v₀, the inductor current i_L1, and the PWM signal v_d for the average-current mode controlled proposed step-up converter with the step changing of the load R being 300 Ω–600 Ω–300 Ω is shown in Figure 9. One can see that the closed-loop controlled proposed step-up converter had good performance.

6. Conclusions

This paper introduces a new step-up converter. The results from theoretical analysis, the Saber simulations, and the circuit experiments show that, even if it has five diodes and five storage elements, it still has the following five good features:

(1)

Although this new step-up converter has five storage elements, that is, three inductors and two capacitors, its averaged model is still fourth-order, because one of the input inductor currents can be expressed by another input inductor current.

(2)

The relation between the inductor L₁ and L₂ has three cases: L₁ = L₂, L₁ < L₂, and L₁ > L₂. However, these relations do not influence its output voltage V₀, i.e., the output voltage V₀ are the same in the three cases.

(3)

Compared to MSTC, ZSC, and SMSTC, the proposed step-up converter has ultrahigh voltage conversion ratio.

(4)

The output voltage of the proposed step-up converter is common-ground and common-polarity with its input voltage, so its value is easy to detect.

(5)

The proposed step-up converter has no abrupt changes in capacitor voltage and inductor current, so it does not suffer from infinite capacitor current and inductor voltage.

Thus, the proposed step-up converter with ultrahigh voltage conversion ratio is a good candidate topology for applications of photovoltaic systems and fuel cell systems, and these applications will be investigated in future work.

Nomenclature of Main Symbols and Variables

Q1, Q2	Power mosfets
D1, D2, D3, D4, D5	Power Diodes
L1, L2, L3 (mH)	Inductors of power stage
C1, C2 (μF)	Capacitors of power stage
R (Ω)	Resistive load
Vramp	Ramp signal
vd (V)	PWM signal
f (kHz)	Switching frequency
d, D, d^	Instantaneous, DC and small signal of duty cycle
vin, Vin, v^in (V)	Instantaneous, DC and small signal of input voltage
T (μs)	Switching period
iL1, iL2, iL3 (A)	Instantaneous values of inductor currents
IL1, IL2, IL3 (A)	DC values of inductor currents
⟨iL1⟩, ⟨iL2⟩, ⟨iL3⟩ (A)	Averaged values of inductor currents
i^L1 , i^L2 , i^L3 (A)	Small signal of inductor currents
ΔiL1, ΔiL2, ΔiL3 (A)	Ripples of inductor currents
vC1, v0 (V)	Instantaneous values of capacitor voltage of C1, C2
⟨vC1⟩, ⟨v0 ⟩ (V)	Averaged values of capacitor voltage of C1, C2
VC1, V0 (V)	DC values of capacitor voltage of C1, C2
v^C1 , v^0 (V)	Small signal of capacitor voltage of C1, C2
ΔvC1, Δv0 (V)	Ripples of capacitor voltage of C1, C2
Gvd(s)	Control-to-output voltage transfer function
Gvv(s)	Input voltage-to-output voltage transfer function
Gi1d(s)	Control-to-inductor current iL1 transfer function
Gi1v(s)	Input voltage-to-inductor current iL1 transfer function
Rvi, Rvd, Rvf, Ri, Rp (kΩ)	Resistors of average current mode controller
Cvf, Cp, Ci (μF)	Capacitors of average current mode controller
Vref (V)	Reference voltage
VL, VU (V)	Lower and upper threshold of ramp signal

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Items	Case 1: L1 = L2	Case 2: L1 < L2	Case 3: L1 > L2
IL1	M2 VinR(1+D)	M2 VinR(1+D)+K1 IL0	M2 VinR(1+D)−K4 IL0
IL2	M2 VinR(1+D)	M2 VinR(1+D)+K2 IL0	M2 VinR(1+D)−K3 IL0
IL3	2M2DVinR(1+D)	2M2DVinR(1+D)+K1 IL0	2M2DVinR(1+D)−K3 IL0
VC1	1+D1−2DVin	1+D1−2DVin	1+D1−2DVin
V0	MVin	MVin	MVin

where IL0 = KD2Vin/(4f(1 − 2D)2), K1 = (D − 2)((D − 1)L1/L2 + 1 + D), K2 = K1 − (2D + L1K(1 − D))(2 − D)(1 − 2D)/D, K3 = (D − 2) ((D − 1) L2/L1 + 1 + D), K4 = K3 − (2D − L2K(1 − D))(2 − D)(1 − 2D)/D.

Items	Case 1: L1 = L2	Case 2: L1 < L2	Case 3: L1 > L2
Q1	MVin	MVin	MVin
Q2	1+D1−2DVin	1+D1−2DVin	1+D1−2DVin
D1	M−12Vin	(M−1)Vin	(M−1)L1 VinL1+L2
D2	2−D1−2DVin	2−D1−2DVin	2−D1−2DVin
D3	M−12Vin	(M−1)L2 VinL1+L2	(M−1)Vin
D4	1+D1−2DVin	1+D1−2DVin	1+D1−2DVin
D5	(2−D)MVin	(2−D)MVin	(2−D)MVin

Items	Case 1: L1 = L2	Case 2: L1 < L2	Case 3: L1 > L2
ΔiL1	D(2−D)TVin(1−2D)L1	D(2−D)TVin(1−2D)L1	D(2−D)TVin(1−2D)L1
ΔiL2	D(2−D)TVin(1−2D)L2	D(2−D)TVin(1−2D)L2	D(2−D)TVin(1−2D)L2
ΔiL3	D(1+D)TVin(1−2D)L3	D(1+D)TVin(1−2D)L3	D(1+D)TVin(1−2D)L3
ΔvC1	2(1−D)M2 VinR(1+D)C1DT	(2(1−D)M2 VinR(1+D)+K2 IL0)DTC1	(2(1−D)M2 VinR(1+D)−K4 IL0)DTC1
Δv0	MVinDTRC2	MVinDTRC2	MVinDTRC2

Case	A	Bd	Bv
Case 1: L1 = L2= L	[00DLD−12L00−1L31−DL3−2DC11C1001−DC2D−1C20−1RC2]	[1+3M−2MD2LVin−ML3Vin−2M2 VinRC1(1+D)−(1−2D)M2 VinRC2(1+D)]	[1+D2L000]
Case 2: L1 < L2	[002DL1+L2D−1L1+L200−1L31−DL3−2DC11C1α2C1α2C11−DC2D−1C20−1RC2]	[1+3M−2MDL1+L2Vin−ML3Vinβ2C1−(1−2D)M2 VinRC2(1+D)]	[1+DL1+L20KD3(L1Kβ4−1)2fC10]
Case 3: L1 > L2	[002DL1+L2D−1L1+L200−1L31−DL3−2DC11C1α3C1α3C11−DC2D−1C20−1RC2]	[1+3M−2MDL1+L2Vin−ML3Vinβ3C1−(1−2D)M2 VinRC2(1+D)]	[1+DL1+L20−KD3(1+L2Kβ4)2fC10]

where α2 = KD3(1 − M − 2L1K(1 + M − MD))/(2f(1 − M)), α3 = − KD3 (1 − M + 2L2K(1 + M − MD))/(2f(1 − M)), β2 = − 2M2Vin/ (R(1 + D)) − 2K1IL0 + 3D2KVin(1 + M(1 − D))(1 − L1K (1 + M(1 − D))/(1 − M))/(2f), β3 = − 2M2Vin/(R (1 + D)) + 2K3IL0 − 3D2KVin (1 + M(1 − D))(1 + L2K(1 + M(1 − D))/ (1 − M))/(2f), β4 = (2(1 + M(1 − D))(1 − M) − (1 + M)2)/(1 − M)2.

Topology	MSTC in [14]	ZSC in [18]	SMSTC in [15]	PSUC
M	D(1−D)(1−2D)	1−D1−2D	11−2D	1+D(1−D)(1−2D)
Switches	2	1	2	2
Diodes	4	1	3	5
Inductors	2	3	1	3
Capacitors	2	3	2	2
Output floating	No	Yes	No	No

Cases	L1 = L2	L1 < L2	L1 > L2
Calculations for V0	90.000 V	90.000 V	90.000 V
Simulations for V0	84.217 V	83.362 V	83.363 V

Author Contributions

F.W. conceived, validated and wrote the manuscript. H.H.-C.I. and J.L. revised the manuscript. All authors contributed to the manuscript.

Funding

This research was funded by the National Natural Science Foundation of China (grant nos. 51377124 and 51521065), the China Scholarship Council (grant no. 201706285022), a Foundation for the Author of National Excellent Doctoral Dissertation of PR China (grant no. 201337), and the New Star of Youth Science and Technology of Shaanxi Province (grant no. 2016KJXX-40).

Conflicts of Interest

The authors declare no conflict of interest.

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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