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Abstract
In accordance with safety requirements of industrial control, a functional safety CPU is designed targeting controller IC used in State Grid. Functional safety verification flow based on FMEDA is setup for the project, which totally comply with IEC61508. In this paper, fault injection with fault simulation and formal analysis flow of functional safety verification is introduced in detail, which is set up for calculation of diagnose coverage on random hardware failure. Employment of formal method completes 2-3 weeks fault analysis in 52 hours, which improved diagnose coverage convergence.
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Details
1 Beijing Smart-Chip Microelectronics Technology Co., Ltd. Beijing, China