Transformer-Less Switched-Capacitor Quasi-Switched Boost DC-DC Converter

Abstract

In this article, a quasi-switched boost converter based on the switched-capacitor technique with high step-up voltage capability is dealt with and analyzed. The proposed converter offers a simple structure and low voltage stress on the semiconductor elements with intrinsic small duty cycle. An inductor of the proposed converter is connected in series with the input voltage source; therefore, continuous input current ripple is attainable. In addition, the efficiency of the proposed converter is also improved. A detailed steady-state analysis is discussed to identify the salient features of the switched-capacitor-based quasi-switched boost DC-DC converter. The performance of the converter is compared against similar existing high boost DC-DC converters. Finally, the switched-capacitor-based quasi-switched boost DC-DC converter is investigated by experimental verification.

1. Introduction

Nowadays, the deployment of the renewable energy sources includes photovoltaic, and fuel cells have grown significantly over the past decade. However, one of the main drawbacks of these sources are low output voltage. As a main part of the distributed generation technologies, the high-voltage boost DC-DC converters have emerged and been the main link to realize an energy transfer from the renewable energy sources [1,2]. Typical isolated converters have been developed to achieve a high voltage conversion with high turns ratio of the high-frequency transformer. Isolated converters including forward, flyback, half/full-bridge, and push–pull structures were presented in [3,4,5,6]. However, they offer problems such as leakage inductance occurred by the secondary side of the HF transformer, showing large voltage and current spikes on semiconductor devices. By contrast, the transformer-less high voltage gain DC-DC configurations are considering suitable solutions for achieving high conversion efficiency and decreasing the cost of system in the power distributed system due to omitting the galvanic isolation transformers. The coupled-inductor-based structures can also produce the solution to improve the voltage gain without galvanic isolation [7,8]. Nonetheless, these converters have to add a snubber-clamped circuitry to reduce leakage inductor energy recovery problems, which increases the cost of the converter.

For the transformer-less DC-DC structures, a conventional boost DC-DC converter is able to provide a boost ability. In the ideal case, the boost converter can realize very high voltage gain. However, the duty cycle is limited due to the non-idealities of the passive components, semiconductor devices, and loss considerations. Therefore, the conventional boost converter is not a suitable solution for high voltage gain applications. In such applications, the cascaded and quadratic boost converters were introduced to achieve high voltage conversion [9,10]. In this case, two or more conventional boost converters are connected in series. The size and weight of these converters will be increased because many switches and gate drivers are required. Furthermore, the voltage conversion of the converter can also be improved by using the switched-inductor technology in [11,12,13]. In the conventional switched-inductor high step-up DC-DC converter, the voltage gain is limited and the semiconductor devices with high voltage ratings are needed, which significantly raises the cost and the size of the converter. The duty cycle of the mentioned conventional boost non-isolated DC-DC is operated in wide range, and the range of duty cycle is varied between 0 and 1. In this case, the high voltage gain can be obtained with large duty cycle value, which causes to produce power loss on power active switches. Moreover, to limit the range of duty cycle operated within (0, 0.5) and improve the voltage gain, the Z-source and quasi-Z source configurations are considered as good solutions [14,15,16,17]. The shortages of these topologies are discontinuous input current and complex topological structure. Instead of considering about adding passive components in the class of the Z-source and quasi-Z-source-based converters, a class of switched-boost and quasi-switched-boost converters were proposed in [18,19]. However, the voltage stress on the semiconductor devices of them is still high and equals to the output voltage. The aforementioned structures can realize high voltage conversion but share a similar problem, which is the requirement of a large number of additional devices. In addition, research of switched-capacitor-based technology has been proposed to produce the high voltage gain, as presented in [20,21,22,23,24]. The switched-capacitor structure has been known with merits such as small size, low-voltage rating on the semiconductor devices, and high voltage density. In [21], a boost DC-DC converter adopting the switched-boost network was introduced with high voltage conversion and low voltage rating on switches. However, the voltage and current stress of diodes are still high. In [22], an extended switched-boost DC-DC was proposed, which incorporated the switched-capacitor network and switched-boost converter with improved the voltage gain and low voltage stress on semiconductor devices [22]. Nevertheless, the input current is discontinuous and the voltage ratio is still not high. The dual-switch boost converter based on the switched-capacitor in [23] has used for one inductor structure, high boost gain, and low voltage stress. However, the input research in [24] has been proposed the solution for the high-step-up topology. By applying an additional diode and capacitor, the voltage charge pumping solution with integrating switched-boost and Z-source networks have been developed with high voltage gain and low voltage rating on components.

In this article, to enhance the practical high-voltage conversion and reduce the duty cycle ratio, a new transformer-less quasi-switched boost DC-DC converter with integrating switched-capacitor network will be determined. The proposed switched-capacitor switched-boost converter has the merit of enhancing voltage gain, achieve low voltage rating on the active switches and high efficiency. The remainder of this article is organized as follows. Section 2 presents the configuration and operating principle of the switched-capacitor quasi-switched boost converter in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In Section 3, the design guideline is explained. The comparison between proposed converter and other high gain topologies is provided in Section 4. Further, the experimental verifications are presented in Section 5. Finally, Section 6 concludes this article.

2. Operating Principle of Proposed SCQSBC

2.1. Power Circuit

The configuration of the proposed SCQSBC converter as depicted in Figure 1 incorporates the quasi-switched boost network and switched-capacitor cell. The converter is composed of two MOSFETs (S₁ and S₂), four diodes (D₀ to D₃), one inductor, and three capacitors (C₀ to C₂). Figure 2 presents the typical waveforms of the SCQSBC in CCM and DCM. In this case, it can be seen that S₁ is turned on 50% of the period, while S₂ is turned on with the duty cycle of D.

2.2. Circuit Analysis in CCM

To determine the operating analysis of the SCQSBC in the CCM, assume that (1) all power components are ideal; (2) capacitors C₀, C₁, and C₂ are enough to induce the constant voltage in one switching period; and (3) the current of an inductor is linear.

Mode I (t₀–t₁ and t₂–t₃): In this mode, the inductor is magnetized by input power supply. MOSFET S₁ is turned on while MOSFET S₂ is turned off. Capacitors C₁ and C₂ are discharged through the output C₀ capacitor. During this mode, diodes D₀ and D₁ are forward-biased, while diodes D₂ and D₃ are reverse-biased. The analysis circuitry of the SCQSBC is depicted in Figure 3a. The following equations can be given:

(1)$\{\begin{array}{c}{v}_L=V_i\\ i_{C01}+i_{C11}=-I_o\end{array}$

Mode II (t₁–t₂): In this mode, the inductor is still magnetized by input power supply and capacitor C₁. MOSFETs S₁ and S₂ are turned on. Capacitors C₁ and C₂ are also discharged through the output C₀ capacitor. During this mode, diode D₀ is forward-biased, whereas diodes D₁, D₂ and D₃ are reverse-biased. The circuitry of the SCQSBC is depicted in Figure 3b. The equations can be obtained:

(2)$\{\begin{array}{c}{v}_L=V_i+V_{C1}\\ i_{C02}+i_{C12}=-I_o\\ i_{C22}-i_{C12}=I_L\end{array}$

Mode III (t₃–t₄): In this mode, the inductor is discharged in series with the input voltage to charge two capacitors C₁ and C₂, while MOSFETs S₁ and S₂ are turned off. During this mode, the diodes D₀ is reversed-bias, whereas diodes D₁, D₂ and D₃ are forward-biased. Capacitor C₀ is transferred an energy through the resistive load. The circuitry of the SCQSBC is depicted in Figure 3c. The mentioned equations are given:

(3)$\{\begin{array}{c}{v}_L=V_i-V_{C1}\\ i_{C03}=-I_o\\ i_{C13}=I_L-i_{C23}\end{array}$

From (1) to (3), the average value of the inductor voltage can be obtained:

(4)$L\frac{d{i}_L}{dt}=\left(0.5-D\right)V_i+D\left(V_i+V_C\right)+0.5\left(V_i-V_C\right)=0$

Applying the DC variable equation to (4), the capacitors voltage and voltage gain of the proposed SCQSBC can be given as follows:

(5)$\{\begin{array}{c}{V}_{C1}=V_{C2}=V_C=\frac{2}{1-2D}{V}_i\\ G=\frac{V_o}{V_i}=\frac{4}{1-2D}\end{array}$

where D is the duty cycle.

An inductor of the proposed SCQSBC is connected directly with an input voltage source, and the expressions of the inductor current is:

(6)$I_L=\frac{4}{1-2D}{I}_o$

From (1) to (3), the currents of capacitors C₀, C₁ and C₂ in mode I, II and III are derived as follows, respectively.

(7)$\{\begin{array}{c}{i}_{C01}=\frac{I_o}{k_C-1}\\ i_{C11}=i_{C21}=\frac{-k_C}{k_C-1}{I}_o\end{array}$

(8)$\{\begin{array}{c}{i}_{C02}=\frac{k_C-2+2D}{2D\left(k_C-1\right)}{I}_o\\ i_{C12}=\frac{2-k_C+4D-8k_{C}D+4k_C{D}^2}{2D\left(k_C-1\right)\left(1-2D\right)}{I}_o\\ i_{C22}=\frac{2-k_C-2D}{2D\left(k_C-1\right)}{I}_o\end{array}$

(9)$\{\begin{array}{c}{i}_{C03}=-I_o\\ i_{C13}=\frac{2\left(1+2D\right)}{\left(1-2D\right)}{I}_o\\ i_{C23}=2I_o\end{array}$

(10)$k_C=\frac{C_2{r}_{C2}\%}{2C_0{r}_{C0}\%}$

where k_C, r_C0%, and r_C2% are the ratio of capacitor C₂ and C₀ currents in mode I, voltage ripple of capacitors C₀ and C₂, respectively.

In mode I, the capacitor C₂ and C₀ currents are determined as:

(11)$\{\begin{array}{c}{i}_{C03}=C_2\frac{\Delta V_C}{\left(0.5-D\right)T}=C_2\frac{r_{C2}\%V_C}{\left(0.5-D\right)T}\\ i_{C13}=i_{C23}=C_0\frac{\Delta V_o}{\left(0.5-D\right)T}=C_0\frac{r_{C0}\%V_o}{\left(0.5-D\right)T}\end{array}$

2.3. Circuit Analysis in DCM

The SCQSBC is operated in DCM when the light load of converter is applied. The operating of the proposed SCQSBC for DCM analysis is verified in four modes. First when switch S₁ is only turned on, second when S₁ and S₂ are on simultaneously, third when S₁ and S₂ are turned off and an inductor current is nonzero, and fourth when the S₁ and S₂ are turned off and an inductor current is zero. The inductor current reduces to zero at time t₄. As shown in Figure 2b, intervals t₀–t₁ and t₂–t₃ are mode I, interval t₁–t₂ is mode II, interval t₃–t₄ is mode III, and interval t₄-t₅ is mode IV. Note that the converter is operated in CCM in mode I to mode III.

Mode I (t₀–t₁ and t₂–t₃): For this mode, the operating of the proposed SCQSBC and equivalent circuit are the same as CCM mode I and also depicted in Figure 3a. From the starting point of this mode (time t₀ and t₂–t₃), the inductor current increases linearly from zero and achieves the maximum value at t₃. The current ripple of inductor in each mode is given:

(12)$\Delta I_1=\Delta I_3=\frac{V_i}{2L}\left(0.5-D\right)T$

Mode II (t₁–t₂): For the mode, the operating of the proposed SCQSBC and circuitry is the CCM analysis mode II. The current ripple of inductor in this mode can be given:

(13)$\Delta I_2=\left(\frac{V_i+V_C}{L}\right)DT$

The maximum current through inductor can be given as follows:

(14)$I_{L,max}=\left(\frac{V_i/2+D{V}_C}{L}\right)T$

Mode III (t₃–t₄): For the mode, the operating of the proposed SCQSBC and equivalent circuit are the same as CCM mode III. The current ripple of inductor in this mode can be given:

(15)$\Delta I_4=\left(\frac{V_i-V_C}{L}\right)D_{x}T$

Mode IV (t₄–t₅): The equivalent circuit is depicted in Figure 3c. Switches S₁ and S₂ are remained off and inductor current is at zero level. The capacitor C_o is discharged through resistive load.

According to the condition of CCM/DCM boundary, we have:

(16)$\overline{I_L}<\Delta I_L/2$

The result of the substitution of (6)–(9) into (11) is as follows:

(17)$k<k_{crit}\left(D\right)$

where k is a normalized boundary of the converter in DCM, and k = 36L/(RT), k_crit = 1 − 4D².

Figure 4 presents the relationship of k_crit and D; the DCM and CCM boundary region is depicted. Then, the converter operates in CCM at the value k > k_crit.

Referring to Figure 2b, the average value of inductor current is given by:

(18)$\overline{I_L}=\Delta I_1\left(\frac{1}{2}+2D_x\right)+\Delta I_2\left(\frac{1}{4}+\frac{D_x}{2}\right)$

According to the volt-second balance property of inductor to (13), D_x is calculated:

(19)$D_x=\frac{V_i/2+D{V}_C}{2\left(V_C-V_i\right)}$

From (6), (18), and (19), the output voltage conversion of the SCQSBC in DCM can be verified by:

(20)$G=\frac{2k+1-2D+\sqrt{4k^2+{\left(1-4D^2\right)}^2}}{2\left[k-D\left(1-2D\right)\left(1+D\right)\right]}$

3. Designed Guideline

3.1. Selection of Inductor

The rated current of inductor can be determined as the input current and given by (6). The inductor value is selected such that the proposed SCQSBC operates in CCM. Considering the operating mode 2 shown in Figure 3c, the ripple current expression for inductor is given as:

(21)$\Delta I_L=\frac{V_C-V_i}{2L\cdot f_s}$

Assuming from (4) and (5) that $\Delta I_L=r_L\%I_L,$ inductance L in the function of inductor current ripple is:

(22)$L=\frac{\left(1+2D\right)V_i^2}{2\left(1-2D\right)r_L\%\cdot f_s\cdot P_o}$

where r_L%, T, and P_o are the inductor current ripple, period, and output power, respectively.

3.2. Selection of Capacitors

Like the parameter design guideline of the inductor, the design of the capacitors can be determined by the rated voltage and capacitance. The rated voltages of the capacitors can be determined from (5). The capacitors in the proposed SCQSBC are designed based on the differential equation of capacitors C₀, C₁, and C₂.

(23)$\{\begin{array}{c}{C}_1\frac{\Delta V_C}{0.5T}=\frac{2\left(1+2D\right)}{1-2D}{I}_o\\ C_2\frac{\Delta V_C}{0.5T}=2I_o\\ C_o\frac{\Delta V_o}{0.5T}=I_o\end{array}$

By considering the maximum ripple voltages of the capacitors, the capacitances of C₁, C₂, and C₀ are determined to be:

(24)$\{\begin{array}{c}{C}_1=\frac{2\left(1+2D\right)T}{\left(1-2D\right)R{r}_C\%}\\ C_2=\frac{2T}{R{r}_C\%}\\ C_0=\frac{T}{2R{r}_C\%}\end{array}$

3.3. Selection of Switching Components

Generally, to select the parameter design of the switching components including power MOSFETs and diodes in operating safety range, the rated voltage and current of the components must be considered greater than the theoretical values. The voltage rating of the MOSFETs and diodes are presented in (25) and current stresses from (26) and (27), respectively.

(25)$\{\begin{array}{c}{V}_{S1}=V_{S2}=\frac{2}{1-2D}{V}_i\\ V_{D0}=V_{D1}=V_{D2}=V_{D3}=\frac{2}{1-2D}{V}_i\end{array}$

(26)$\{\begin{array}{c}{I}_{S1}=\frac{3-2D}{1-2D}{I}_o\\ I_{S2}=\frac{4}{1-2D}{I}_o\end{array}$

(27)$\{\begin{array}{c}{I}_{D0}=I_o\\ I_{D1}=\frac{4}{1-2D}{I}_o\\ I_{D2}=\frac{2\left(1+2D\right)}{1-2D}{I}_o\\ I_{D3}=2I_o\end{array}$

3.4. Power Loss Analysis

In this section, the power loss of the proposed SCQSBC topology is investigated. The power loss calculation can be validated according to conducting time and conducting current of devices, as shown in Table 1. The power loss distribution is included the MOSFETs, diodes, inductor, and capacitors loss. The power loss of MOSFETs can be given:

(28)$\begin{array}{c}{P}_M=P_{Con\_S1}+P_{Sw\_S1}+P_{Con\_S2}+P_{Sw\_S2}\\ =\frac{\left(9+20D+4D^2\right)}{2{\left(1-2D\right)}^2}\cdot I_o^2\cdot R_{DSon}+\frac{\left(7-2D\right)}{{\left(1-2D\right)}^2}\cdot V_i\cdot I_o\cdot f_s\cdot \left(t_{on}+t_{off}\right)\end{array}$

where R_DSon, f_s, t_on, and t_off are the on-state drain-source resistance, switching frequency, and the turn-on and turn-off times, respectively.

The diode power loss is included the conduction loss and the reverse recovery loss.

(29)$P_D=P_{Con\_D}+P_{Sw\_D}$

The conduction loss of D₀, D₁, D₂ and D₃ diodes is calculated as:

(30)$\begin{array}{c}{P}_{Con\_D}={\displaystyle \sum _{x=0}^3}{P}_{Con\_Dx}=\left(u_D\cdot I_o+r_D\cdot I_o^2\right)\cdot 0.5+\left[u_D\cdot \frac{4I_o}{1-2D}+r_D\cdot {\left(\frac{4I_o}{1-2D}\right)}^2\right]\cdot 0.5\\ +\left[u_D\cdot \frac{2\left(1+2D\right)I_o}{1-2D}+r_D\cdot {\left(\frac{2\left(1+2D\right)I_o}{1-2D}\right)}^2\right]\cdot \left(1-D\right)+\left[u_D\cdot 2I_o+r_D\cdot 4I_o^2\right]\cdot 0.5\end{array}$

where u_D and r_D are the ON-state voltage and the ON-state resistance of diodes, respectively.

The reverse recovery loss of diodes is given:

(31)$P_{Sw\_D}={\displaystyle \sum }_{x=0}^3{P}_{Sw\_Dx}=4Q_{rr}\cdot \frac{2V_i}{1-2D}\cdot f_s$

where Q_rr is the reverse recovery charge of diodes.

Power loss of capacitors can be derived by:

(32)$P_C=r_{C0}\cdot i_{C0\_rms}^2+r_{C1}\cdot i_{C1\_rms}^2+r_{C2}\cdot i_{C2\_rms}^2$

The RMS current of C₀, C₁ and C₂ capacitors are derived as:

(33)$\{\begin{array}{c}{i}_{C0\_rms }=\sqrt{I_o^2\cdot \left(0.5-D\right)+{\left[\frac{2\left(1+2D\right)I_o}{1-2D}\right]}^2\cdot D+4I_o^2\cdot 0.5}\\ i_{C1\_rms }=\sqrt{{\left(\frac{I_o}{k_C-1}\right)}^2\cdot D+{\left(\frac{k_C}{k_C-1}{I}_o\right)}^2\cdot \left(1-D\right)}\\ i_{C2\_rms }=\sqrt{{\left[\frac{\left(k_C-2+2D\right)I_o}{2D\left(k_C-1\right)}\right]}^2\cdot \left(0.5-D\right)+{\left[\frac{\left(2-k_C+4D-8k_{C}D+4k_C{D}^2\right)I_o}{2D\left(k_C-1\right)\left(1-2D\right)}\right]}^2\cdot D+{\left[\frac{\left(2-k_C-2D\right)I_o}{2D\left(k_C-1\right)}\right]}^2\cdot 0.5}\end{array}$

Power loss of inductor can be given by:

(34)$P_L=P_{fe}+P_{cu}=k\cdot B^{\beta }\cdot f_s^{\alpha }\cdot A_e\cdot l_e+r_L\cdot I_{L\_RMS}^2$

where B is the AC magnetic flux; f_s is the frequency; A_e is the core cross-sectional area; l_e is the core mean magnetic path length; I_{L_rms} is RMS current of the inductor; and r_L is wire resistance. k, α, β can be found from the manufacturer’s datasheet.

4. Comparison with Other High Gain DC-DC Converter

4.1. Voltage Gain and Count of Device Comparison

In this section, the comparison of the performance of the proposed SCQSBC with other high voltage gain converters is reported. Table 2 presents the comparison count of devices used in these converters. According to Table 2, it can be seen that the proposed SCQSBC has one less inductor than AQSC [21] and VPQBC [24], and two less inductors than 3-ZBC [17]. Moreover, it has two less capacitors than the AQSC [21]. Besides, the total number of devices of the proposed converter has the same with the ESBC [22], SCDSC [23], VPQBC [24], and VPQSBC [24], and less than those of the 3-ZBC [17] and AQSC [21].

The expressions of the voltage gain comparison of the proposed SCQSBC and those of the other high gain converters are shown in Table 2 and also mentioned in Figure 5a. It can be found that the gain of proposed SCQSBC is the highest in compared with other converters through the whole duty cycle lower than 0.33.

4.2. Voltage and Current Stress Comparison

The detailed voltage and current rating of the proposed SCQSBC and other converters have been shown in Table 2 to make the comparison. It can be seen that the total normalized voltage and current stress of semiconductor devices have been depicted in Figure 5b,c. From Figure 5b, the switch voltage stress of the proposed SCQSBC is the same as those of the VPQSBC [24] and 3-ZBC [17]. Besides this, it is lower than the switch voltage stress of the VPQBC [24] and higher than those of the ESBC [22], SCDSC [23], and AQSC [21]. Moreover, the diode voltage stress of the proposed SCQSBC and VPQSBC is higher than ESBC [22] and lower than those of other converters.

Figure 5d,e depict the plots of the current stress of switches and diode with other converters. It can be seen that the switch current stress of the proposed SCQSBC is lower than that of the AQSC [21], ESBC [22], SCDSC [23], and VPQSBC [24]. However, the SCQSBC has higher switch current stress than that of the 3-ZBC [17] and VPQBC [24]. This is because they only used one switch. In the diode current stress comparison, the diode current stress of VPQSBC is the lowest. Moreover, the SCQSBC is lower than that of the 3-ZBC [17] and AQSC [21]. AQSC [21], ESBC [22], SCDSC [23], and VPQBC [24] in the whole voltage gain from 0 to 7.4.

4.3. Input Current and Inductor Current Ripple Comparison

Based on Table 2, Figure 5f draws the inductance value curves versus output voltage gain among the mentioned converters. It can be noticed that the inductance of the proposed SCQSBC is lower than that of the 3-ZBC, VPQBC, SCDSC, VPQBC, and AQSC. This makes the size of the magnetic element of the proposed SCQSBC small. Note that the inductance comparison was calculated with applying the same operating condition of input voltage, output power, switching frequency, and inductor current ripple. As summarized in Table 2, the input current ripple is considered for comparison. The diode and capacitor are directly connected to the input voltage source in the 3-ZBC, ESBC, and SCDSC, leading to the occurrence of very high input current ripple in these topologies. In the remaining converters, the input current is equal to the inductor current, so it can be observed that the input current ripple of the proposed SCQSBC is the lowest.

5. Simulation and Experimental Results

In order to verify the precision of the operating capability of SCQSBC, some simulation and experiments have been conducted. For simulation verification, a simulation is built for the SCQSBC parameters are follows: V_i = 20 V (D = 0.3) and V_i = 50 V (D = 0), V_o = 200 V, P_o = 250 W, L = 0.5 mH, C₁ = C₂ = 10 µF, C₀ = 110 µF, and all semiconductor devices are ideal. The switching frequencies are 20 kHz and 50 kHz have been tested in the simulation. In two cases, output voltage V_o is 200 V and the voltage stresses across all semiconductor devices and average value of capacitors voltage are half of the output voltage, as shown in Figure 6 and Figure 7. However, the peak-to-peak values of inductor L current and capacitors C₁, C₂ voltage are increased when the switching frequency is reduced, which are consistent with the calculations obtained in (22) and (24).

The experimental prototype was also designed and shown in Figure 8. The key parameters for the experiment are presented in Table 3. Two power MOSFETs of IRFP4668PbF with low values of r_DSon and four Schottky STPS60SM200C diodes were considered to use for the laboratory prototype. The experimental results with the input voltage of 50 V are depicted in Figure 9a,c,e. The obtained waveforms of PWM signals and drain-source of switches S₁ and S₂ are shown in Figure 9a. The switch S₁ has 50% on-state and off-state, while switch S₂ is turned off. In this case, the duty cycle D is zero. The average and peak values of the voltage across switch S₁ are 52 V and 100 V, respectively. The switch S₂ is always off with the peak voltage stress of 100 V. The measured output voltage, capacitor C₁, C₂ voltage, and input current are 201 V, 100.5 V, 101 V, and 4.3 A, respectively. It can be observed that the input current is continuous with a small ripple, and the peak-to-peak inductor current ripple is 0.85 A. The slope of the input current is magnetizing and demagnetizing due to the on-state of switch S₁. The waveform of voltage across the D₀, D₂ and D₃ diodes are reversed-bias with the peak value of 100 V, while the D₁ diode is always forward-bias, as depicted in Figure 9e. In another case, the converter has been tested with 20 V DC input voltage and the duty cycle is set 0.3, as shown in Figure 9b,d,f. The PWM control signals for S₁ and S₂ are also observed and depicted in Figure 9b, where switch S₁ is still 50% on-state and off-state. However, switch S₂ is turned on with a duty cycle of 0.3. The average and peak values of the voltage rated switch S₁ are 52 V and 101 V, respectively. For switch S₂, the obtained average and peak values of the voltage across switch S₂ are 72 V and 100 V, respectively. It can be obtained that 200.5 V output voltage is produced and the input current is also continuous with the peak-to-peak inductor current ripple of 1.83 A, and the inductor is just demagnetized due to the off-state of switch S₁. As depicted in Figure 9f, the voltage stress of the D₀, D₁, D₂, and D₃ diodes are 100 V.

Based the analysis in Section 3.4 and the parameters in Table 4, the power loss calculation of the proposed SCQSBC is validated. The power loss distribution is depicted in Figure 10 with the input voltages are 20 V and 50 V. It can be observed that the duty cycle is large when V_i = 20 V leads to decrease the efficiency of the converter. When the input voltage with 50 V is applied, the efficiency is significantly increased. As shown in Figure 10, the power loss of the diode is highest in the loss distribution; this is because the four diodes were used in the proposed SCQSBC. Table 5 shows the measurement current input ripple and peak-to-peak inductor current ripple and efficiency the proposed SCQSBC and other switched-capacitor-based converters in [24]. In this experiment, the input voltage and output power rating are tested in 20 V and 200 W. It can be seen that the peak-to-peak inductor current ripple of the proposed converter is the lowest. Furthermore, the proposed converter can reduce the size of the inductor of the design when compared with other converters. The input current ripple of the proposed converter is also the lowest.

The measured efficiencies of ESBC [22], SCDSC [23], and VPQBC–VPQSBC [24] are highlighted compared with the proposed SCQSBC because they used the same number of components with the proposed SCQSBC. To validate the measured efficiency, the experimental parameters in Table 3 are used for specification of the ESBC [22], SCDSC [23], VPQBC–VPQSBC [24], and the proposed SCQSBC. The plot of measurement efficiency versus output power of the proposed converter and other converters are shown in Figure 11 when the input voltages are 20 V and 50 V. In this case, the output power is measured from 80 W to 250 W. When V_i = 50 V, the proposed SCQSBC achieves the highest efficiency of 97%. When the input voltage is reduced to 20 V, the efficiency of the proposed converter is greater than that of other converters in comparison.

The simple PI controller for output voltage loop has been determined to generate the output voltage is 200 V, as shown in Figure 12. The experimental results are shown under the load transient between light load and full load while input and output voltage are 20 V and 200 V, respectively. Moreover, the input voltage adjustment is also considered from 20 V to 50 V. In this case, the output voltage and power are set at 200 V and 200 W, respectively. As depicted in Figure 13, it can be observed that the output voltage of the proposed SCQSBC is insensitive to the load in Figure 13a or input voltage variation in Figure 13b, and settling time of the converter is approximately 0.1 s.

6. Conclusions

A switched-capacitor-based quasi-switched boost DC-DC converter is presented in this article for low power and high step-up voltage conversion applications. The contributions of the SCQSBC include: providing a high voltage capability with small duty cycle, thereby improving the efficiency of the converter; and a simple topological structure. Moreover, the low input current ripple of the SCQSBC can maintain the lifetime of the power DC sources in renewable energy systems. The theoretical analysis in CCM/DCM boundary condition and parameters design are determined in detail. What is more, the performance comparisons with other transformer-less high gain structures and an experimental verification with single closed-loop controller are provided to demonstrate the characteristics of the proposed SCQSBC. The proposed SCQSBC was suitable for interfacing fuel cells and photovoltaic applications, which required high voltage gain.

Author Contributions

T.-D.D. determined topology, conducted data analysis, and prepared the original draft. M.-K.N. contributed to review and editing. T.-T.T. contributed to validating the simulation and experimental work. Y.-C.L. provided resources and supervision. J.-H.C. provided resources and funding acquisition. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

This research was supported by “Regional Innovation Strategy (RIS)” through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (MOE) (2021RIS-002).

Conflicts of Interest

The authors declare no conflict of interest.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Figures and Tables

Figure 1. Proposed SCQSB converter.

Figure 2. Typical waveform of proposed SCQSBC for (a) CCM and (b) DCM.

Figure 3. Operating modes of proposed SCQSBC: (a) Mode I, (b) Mode II, (c) Mode III, and (d) Mode IV (DCM).

Figure 3. Operating modes of proposed SCQSBC: (a) Mode I, (b) Mode II, (c) Mode III, and (d) Mode IV (DCM).

Figure 4. CCM/DCM boundary condition of the SCQSBC.

Figure 5. Comparison between the proposed converter and other converters: (a) Voltage gains versus duty cycle, (b) Total voltage rating of switches, (c) Total voltage rating of diodes, (d) Total current rating of switches, (e) Total current rating of diodes, and (f) Inductance.

Figure 5. Comparison between the proposed converter and other converters: (a) Voltage gains versus duty cycle, (b) Total voltage rating of switches, (c) Total voltage rating of diodes, (d) Total current rating of switches, (e) Total current rating of diodes, and (f) Inductance.

Figure 6. Simulation results with Vi = 50 V: (a,b) fs = 20 kHz and (c,d) fs = 50 kHz. From top to bottom: input voltage, output voltage, capacitors C1, C2 voltage; inductor current; the drain-source of switch S1 and S2; diodes D0, D1, D2 and D3 voltage stress.

Figure 7. Simulation results with Vi = 20 V: (a,b) fs = 20 kHz and (c,d) fs = 50 kHz. From top to bottom: input voltage, output voltage, capacitors C1, C2 voltage; inductor current; the drain-source of switch S1 and S2; diodes D0, D1, D2 and D3 voltage stress.

Figure 8. Prototype of proposed SCQSBC.

Figure 9. Experimental results with Vi = 50 V (left side) and 20 V (right side). (a,b) Bottom to top: The drain-source and gate-source voltage of switch S1 and S2; (c,d) output voltage, capacitors C1, C2 voltage, inductor current; (e,f) diode D3, D2, D1 and D0 voltage stress.

Figure 9. Experimental results with Vi = 50 V (left side) and 20 V (right side). (a,b) Bottom to top: The drain-source and gate-source voltage of switch S1 and S2; (c,d) output voltage, capacitors C1, C2 voltage, inductor current; (e,f) diode D3, D2, D1 and D0 voltage stress.

Figure 10. Power loss distribution.

Figure 11. Measured efficiency comparison at (a) Vi = 20 V, and (b) Vi = 50 V.

Figure 12. Simple PI controller for the proposed SCQSBC.

Figure 13. Experimental results with closed-loop control. (a) The load change and (b) Input voltage change.

Table 1

Conducting current and period of devices.

Components	Conducting Current	Conducting Period
S 1	$$\frac{3-2D}{1-2D}{I}_o$$	0.5 × T
S 2	$$\frac{4}{1-2D}{I}_o$$	D × T
D 0	Io	0.5 × T
D 1	$$\frac{4}{1-2D}{I}_o$$	(1 − D) × T
D 2	$$\frac{2\left(1+2D\right)}{1-2D}$$	0.5 × T
D 3	2Io	0.5 × T
L	$$\frac{4}{1-2D}{I}_o$$	T
C 1	$$\frac{I_o}{k_C-1}$$	D × T
	$$\frac{-k_C}{k_C-1}{I}_o$$	(1 − D) × T
C 2	$$\frac{k_C-2+2D}{2D\left(k_C-1\right)}{I}_o$$	(0.5 − D) × T
	$$\frac{2-k_C+4D-8k_{C}D+4k_C{D}^2}{2\left(k_C-1\right)D\left(1-2D\right)}{I}_o$$	D × T
	$$\frac{2-k_C-2D}{2D\left(k_C-1\right)}{I}_o$$	0.5 × T
Co	−Io	(0.5 − D) × T
	$$\frac{2\left(1+2D\right)}{1-2D}{I}_o$$	D × T
	2Io	0.5 × T

Table 2

Comparison of the proposed SCQSBC topology with considered topologies.

	3-ZBC [17]	AQSC [21]	ESBC [22]	SCDSC [23]	VPQBC [24]	VP-QSBC [24]	Proposed SCQSBC
Inductor/Capacitor	4/2	2/4	1/3	1/3	2/3	1/3	1/3
Switch/Diode	1/9	2/4	2/4	2/4	1/4	2/4	2/4
Total of Devices	16	12	10	10	10	10	10
Voltage gain	$${\left(\frac{1+D}{1-D}\right)}^2$$	$$\frac{2\left(1-D\right)}{1-3D+D^2}$$	$$\frac{2\left(1-D\right)}{1-2D}$$	$$\frac{3-2D}{1-2D}$$	$$\frac{2-D}{{\left(1-D\right)}^2}$$	$$\frac{2}{1-2D}$$	$$\frac{4}{1-2D}$$
Normalized capacitor voltage stress (VC/Vi)	$$\frac{1+D}{1-D}$$ $${\left(\frac{1+D}{1-D}\right)}^2$$	$$\frac{D}{1-3D+D^2}$$ $$\frac{1-D}{1-3D+D^2}$$ $$\frac{2\left(1-D\right)}{1-3D+D^2}$$	$$\frac{D}{1-2D}$$ $$\frac{1-D}{1-2D}$$ $$\frac{2\left(1-D\right)}{1-2D}$$	$$\frac{1}{1-2D}$$ $$\frac{3-2D}{1-2D}$$	$$\frac{1}{1-D}$$ $$\frac{1}{{\left(1-D\right)}^2}$$ $$\frac{2-D}{{\left(1-D\right)}^2}$$	$$\frac{1}{1-2D}$$ $$\frac{2}{1-2D}$$	$$\frac{2}{1-2D}$$ $$\frac{4}{1-2D}$$
Normalized switch voltage stress (VS/Vi)	$${\left(\frac{1+D}{1-D}\right)}^2$$	$$\frac{D}{1-3D+D^2}$$ $$\frac{1-D}{1-3D+D^2}$$	$$\frac{D}{1-2D}$$ $$\frac{1-D}{1-2D}$$	$$\frac{1}{1-2D}$$	$$\frac{1}{{\left(1-D\right)}^2}$$	$$\frac{1}{1-2D}$$	$$\frac{2}{1-2D}$$
Normalized diode voltage stress (VD/Vi)	D/(1 − D)12D(1 + D)/(1 − D)2(1 + D)/(1 − D)D(1 + D)/(1 − D)2(1 + D)2/(1 − D)2	$$\frac{1}{1-3D+D^2}$$ $$\frac{1-D}{1-3D+D^2}$$	$$\frac{1-D}{1-2D}$$ $$\frac{D}{1-2D}$$	$$\frac{2}{1-2D}$$ $$\frac{1}{1-2D}$$	$$\frac{1}{{\left(1-D\right)}^2}$$ $$\frac{1}{1-D}$$ $$\frac{D}{{\left(1-D\right)}^2}$$	$$\frac{1}{1-2D}$$	$$\frac{2}{1-2D}$$
Switch current stress (IS/Io)	$$\frac{4D}{{\left(1-D\right)}^2}$$	$$\frac{2}{1-3D+D^2}$$ $$\frac{1+D-D^2}{D\left(1-3D+D^2\right)}$$	$$\frac{2}{1-2D}$$ $$\frac{1}{D\left(1-2D\right)}$$	$$\frac{1}{D\left(1-2D\right)}$$	$$\frac{1+D-D^2}{D{\left(1-D\right)}^2}$$	$$\frac{2}{1-2D}$$ $$\frac{1}{D\left(1-2D\right)}$$	$$\frac{3-2D}{1-2D}$$ $$\frac{4}{1-2D}$$
Diode current stress (ID/Io)	D(1 + D)/(1 − D)2(1 + D)/(1 − D)2D(1 + D)/(1 − D)2D/(1 − D)1	1/D$$\frac{2}{1-3D+D^2}$$$$\frac{1}{1-D}$$	1/D$$\frac{1}{1-3D+2D^2}$$$$\frac{1}{1-D}$$$$\frac{2}{1-2D}$$	1/D$$\frac{1}{1-D}$$$$\frac{2}{1-2D}$$$$\frac{1}{\left(1-D\right)\left(1-2D\right)}$$	1/D$$\frac{2-D}{{\left(1-D\right)}^2}$$$$\frac{1}{1-D}$$	1/D$$\frac{D}{\left(1-D\right)\left(1-2D\right)}$$$$\frac{1}{1-D}$$	1$$\frac{4}{1-2D}$$$$\frac{2\left(1+2D\right)}{1-2D}$$2
Inductances	$$D\left(1+D\right)k_L$$ $$\frac{D{\left(1+D\right)}^3}{{\left(1-D\right)}^2}{k}_L$$	$$\frac{2D{\left(1-D\right)}^2}{1-3D+D^2}{k}_L$$	$$\frac{D{\left(1-D\right)}^2}{1-2D}{k}_L$$	$$\frac{D\left(1-D\right)\left(3-2D\right)}{1-2D}{k}_L$$	$$\frac{D\left(2-D\right)}{1-D}{k}_L$$ $$D{k}_L$$	$$\frac{2D\left(1-D\right)}{1-2D}{k}_L$$	$$\frac{1+2D}{2\left(1-2D\right)}{k}_L$$
Input current ripple	High	Low	High	High	Low	Low	Very low

k_L is coefficient of inductor.

Table 3

Experimental parameters.

Parameter	Values
Input voltage range	20 V to 50 V
Output voltage	200 V
Power rating	250 W
Inductor (L)	0.5 mH
Capacitors	10 µF/160 V for C1, C2
	110 µF/450 V for C0
Switching frequency	50 kHz
MOSFETs	IRFP4668PbF
Diodes	STPS60SM200C

Table 4

Parameters for power loss analysis.

Parameters		Values
Inductor	Core	CM777125 (142 nH/N2)
	Copper-wire	0.04 Ω
Capacitors	C1, C2	3.2 mΩ
	Co	4 mΩ
Power switches		IRFP4668PbF (200 V, 130 A, RDSon = 8 mΩ)
Power diodes		STPS60SM200C (200V, 30A, UD = 0.7 V)

Table 5

Input current ripple and efficiency of VPQBC, VPQSBC, and proposed SCQSBC at V_i = 20 V and P_o = 250 W.

Converter	VPQBC	VPQSBC	Proposed SCQSBC
ΔIin	1.3 A	1.2 A	0.8 A
Efficiency	91.1%	90.9%	91.8%

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