Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design

Abstract

Implementing stateful logic based on memristors is a promising approach for the development of a highly efficient in-memory computing paradigm, wherein the data transmission between the controller and memory is largely alleviated. However, the deviation of the electrical behavior of memristors causes errors in the execution process of the stateful logic. Consequently, a reliability issue arises that must be carefully addressed. Here, a method of error detection and correction (EDC) based on memristor-based stateful logic operation is proposed for the IMP stateful logic gate (PMR-two-2IMP). Leveraging the concept of redundancy, error detection is achieved with the assistance of a stateful NOR logic gate, while a composite stateful OR logic gate is used for error correction. In the simulated validation, the concept of redundancy is employed to improve the accuracy of EDC. Finally, the feasibility of the proposed method for practical devices (TiN/TaO_x/HfO_x/TiN) is demonstrated using a circuit platform equipped with a 1T1R crossbar array.

Introduction

Memristor-based stateful logic is an efficient in-memory computing paradigm, where both the source and destination operands are represented by the resistive states of the memristor, and the logic operation is performed in situ within the same memristor circuit.^{[ 1–5 ]} To date, many stateful logic gates based on various circuit structures have been proposed.^{[ 6–12 ]} According to the naming rule proposed by Xu et al.,^{[ 13 ]} the “Structure-N-n Function” format is used to define different types of stateful logic gates, among which, 2 parallel memristors + a series resistor for two inputs imply logic (PMR-two-2IMP),^{[ 10 ]} 3 parallel memristors + a series resistor for two inputs nor logic (PMASM-two-3NOR),^{[ 11 ]} and 2 parallel memristors + 1 anti-serial memristor for two inputs nor logic (PMASM-two-3NOR)^{[ 12 ]} are the classical gates that have received extensive attention in both experiments and applications.^{[ 14–23 ]}

The stateful logic operation is inherently based on the conditionally resistive switching of the resistance states under a group of fixed control voltages. The successful execution of conditionally resistive switching depends on the uniformity of the resistance states and the threshold switching voltages of the device.^{[ 24–27 ]} However, at the present developmental stage of technology, the memristor is limited by the variations in switching voltage and device resistance. Consequently, the execution of a stateful logic gate usually leads to unexpected errors.^{[ 28–34 ]} Therefore, before the stateful logic is practically implemented, the logic operating reliability issue should be resolved by developing an appropriate method to correct unexpected operating errors at the gate level.^{[ 35 ]} Recently, some peripheral complementary metal-oxide-semiconductor (CMOS) circuit-based error detection and correction (EDC) methods for stateful logic gates have been proposed.^{[ 36–38 ]} Although there are several approaches to check and correct the operation errors of a single stateful logic gate, there are several adverse factors that impact the practical use of stateful logic. First, these methods alter the computing paradigm from in-memory computing to near-memory computing. The data are read out of the memory array to complete the EDC process. This process restores the partial energy consumption of data movement that is saved by stateful logic operations. Second, the peripheral CMOS circuit promotes various limitations,^{[ 39,40 ]} for example, area and energy consumption for logic execution, and is particularly unsuitable for the parallel execution of stateful logic gates. If the EDC is to be performed for the multiple parallelly executed stateful logic gates, a corresponding number of CMOS check and correction circuit is required that is a heavy encumbrance for realization, considering the significant parallelism of the stateful logic operations in the crossbar array. In addition, the computing power of the peripheral CMOS correction circuit is similar to that of the corrected stateful logic gate that renders the stateful logic gate unnecessary and higher efficiency may be realized when the peripheral CMOS circuit is used for computing directly. To address these issues, an EDC approach based on the cascading of stateful logic gates should be implemented for eliminating the cost of CMOS circuits and maintaining the in-memory computing paradigm in the entire process.

In this article, an EDC method for the material implication (IMP) stateful logic gate (PMR-two-2IMP) based on memristor is proposed. For the PMR-two-2IMP gate, the possible errors of practical devices during logic execution are analyzed, and the potential errors are effectively controlled by adjusting the voltage application scheme. Thereafter, an error detection method and error correction method based on stateful logic operations are proposed by leveraging the concept of redundancy and error control scheme. Finally, the proposed methods are verified by SPICE simulation and implemented on a circuit platform equipped with a 1T1R crossbar array.

It should be noted that the error in this study is limited to the execution result of a single stateful logic gate, wherein the main sources are the cycle-to-cycle and device-to-device variations of the device parameters, owing to the probabilistic ion movement or the randomized defects presented in the device matrix. In this assumption, the logic input data are reliable, although the actual resistance values might fluctuate within an allowable range of the high resistance state (HRS) or low resistance state (LRS). The proposed EDS method ensures the correctness of the execution result of a PMR-two-2IMP gate when the fluctuation (not inversion) of the resistance values of the input data and the variations of the device parameters are considered. The other errors, such as the errors or inversions of the input data resulting from the poor retention property of the device and the influence of the execution of the other gate in the same crossbar array, will be considered in future work. A stateful ECC can also be used to solve the reliability of the input data.^{[ 41 ]}

Preliminaries Device Property

After fabrication, the crossbar array device was plastic-packaged in a quad flat package (QFP-100) format for further utilization. To measure the device properties and verify the performance of the proposed EDC method, we developed a circuit-level platform where the TiN/TaO _x /HfO _x /TiN 1T1R crossbar array and its peripheral circuits were included. An illustration of the circuit platform is presented in Figure S1 (Supporting Information). The details of the array fabrication are described in the experimental section. For the 1 kb 1T1R array, the transistor is utilized as a selector to avoid the sneak path issue and a current limiter to implement the compliance current. In the DC sweeping test, as shown in Figure  1a, the switching behavior of the device exhibits the classical I–V characteristic of a bipolar memristor, where the resistance switching is sensitive to the polarity and magnitude of the applied voltage. When the selected memristor is set to the LRS, the selected SL is turned on, and the selected WL sweeps from 0 to 2 V, while the BL is grounded. During the reset operation in which the selected memristor is reset to the HRS, the selected SL is turned on, and the selected WL is grounded, while the selected BL sweeps from 0 to 2 V to achieve negative voltage polarity. The distribution of the resistance states is obtained by testing 100 cycles and reading the resistance at 0.5 V after each switching step, as shown in Figure 1b. The resistance value R _HRS of HRS mainly fluctuates between 80 and 130 kΩ, and the resistance value R _LRS of LRS mainly fluctuates between 10 and 30 kΩ. Figure 1c shows the distribution of threshold voltage V _set with an average value μ = 1.25 V and variance σ = 0.021 V.

FIGURE: DC characterization of TiN/TaO _x /HfO _x /TiN memristor. a) Switching behaviors of the bipolar memristor. The voltage polarity is defined by V _WL–V _BL. b) DC cumulative curves of HRS and LRS. c) Distribution of threshold voltage V _set for set operation.

Considering stateful logic applications, the memristor cells were also measured in the pulse test. During pulse set operation, a pulse with an amplitude of 1.5 V and width of 100 μs was applied on the selected WL. During the pulse reset operation, the amplitude and width of the reset pulse on the selected BL were 2 V and 100 μs, respectively. The corresponding test results of the R _LRS and R _HRS distributions are shown in Figure  2a,b, respectively. Thereafter, the logic values are mapped onto separate resistance intervals defined by the intrinsic variability. Logic “0” is mapped to a resistance larger than 80 kΩ, while logic “1” corresponds to a resistance lower than 50 kΩ.

FIGURE: Performance of device variation in pulse test. a) R _LRS distribution measured in the pulse set operation. b) R _HRS distribution measured in the pulse reset operation.

PMR-two-2IMP Gate

As shown in Figure  3a, the IMP ($P\to Q=\overline{P}+Q$) function can be realized by a simple circuit that consists of two parallel memristors P and Q and one resistor R _L, where the resistances are in the order LRS < R _L < HRS. Along with the control voltages, this circuit structure is called a PMR-two-2IMP gate.^{[ 13 ]} Any complicated Boolean logic function can be realized by cascading the stateful logic gate and the false (reset) operation.

FIGURE: Principle of establishing PMR-two-2IMP gate. a) Schematic of the PMR-two-2IMP gate unit. b) IMP logic function realized based on the bias condition and conditional switching. c) Simulation results of PMR-two-2IMP success rate as a function of V _Q, when V _P = 1.2 V, for all inputs.

To perform the IMP logic function, as shown in Figure 3b, two positive voltage pulses of V _P with an amplitude lower than V _set, and V _Q with an amplitude larger than V _set, are applied to P and Q, respectively. Only when both P and Q are in HRS (logic “‘0”), the node voltage V _int is sufficiently small for the voltage across memristor Q larger than V _set to change the resistance state of Q to LRS (logic “1”). Otherwise, the resistor R _L divides a sufficiently large voltage V _int, and the voltage across Q is smaller than V _set, such that the resistance state of Q remains unchanged.

Three types of unexpected errors of stateful logic, including unintended nonswitching of the output memristor, unintended switching of the output memristor, and unintended switching of the input memristor, are caused by device variation.^{[ 37,38 ]} Setting V _P = 1.2 V, detailed analyses of the voltage drop across memristors P and Q for different inputs are shown in Figure S2 (Supporting Information). For the PMR-two-2IMP gate, the unintended nonswitching of the output memristor Q occurs when both inputs are “0,” and the unintended switching of the output memristor Q occurs when P = “1,” Q = “0.” The success rates of the PMR-two-2IMP gate operation as a function of V _Q are simulated through HSPICE simulation with the modified TEAM model^{[ 42,43 ]} and the transistor model provided by the commercial CMOS foundry; the results of all inputs are shown in Figure 3c. It is difficult to establish an appropriate method to implement EDC when multiple error types exist simultaneously. Thus, the error cases are usually required to be controlled and limited to only one specific input, even if it increases the error rate of the single-error case. To control the type of logic error, the value of the applied voltage V _Q should be restricted below 2.1 V.

Stateful Logic-Based EDC Method for PMR-two-2IMP

After restraining the error of the PMR-two-2IMP gate to the specific input (0, 0), two auxiliary memristors are added to the PMR-two-2IMP gate for increasing the accuracy of the logic execution by introducing the EDC processes, as shown in Figure  4a. Figure 4b shows the workflow including logic execution and EDC processes: 1) memristors P and Q are used to construct a PMR-two-2IMP gate in which Q is used as the output memristor; 2) P, Q, and the auxiliary memristor Z ₁ are used to construct a PMR-two-3NOR gate to perform error detection, where the detection result is stored in Z ₁; 3) P, Q, and the auxiliary memristor Z ₂ are used to construct a PMR-two-3NOR gate to perform error detection. This step is used to introduce the redundancy of the detection result; and 4) the error correction for the PMR-two-2IMP gate is implemented through the composite PMR-three-3OR gate constructed using Z ₁, Z ₂, and Q.

FIGURE: Proposed EDC method for PMR-two-2IMP. a) Circuit diagram, A: PMR-two-2IMP part, B: error detection part, and C: error correction part. b) Processing flow of EDC.

Because the error of the PMR-two-2IMP gate is restrained to the input of (0,0), the error detection for the PMR-two-2IMP gate is equivalent to assessing whether the combination of P and Q is (0,0) after the logic operation.^{[ 38 ]} This detection can be achieved by utilizing a PMR-two-3NOR gate, whose circuit diagram and truth table are shown in Figure  5a,b, respectively. The output of PMR-two-3NOR gate is “1,” that is, the set process of the output memristor Z will occur only when all the inputs are “0.” Otherwise, Z remains “0” for other input combinations. Therefore, the error detection of the PMR-two-2IMP gate can be achieved by constructing a PMR-two-3NOR gate, as described in steps 2) and 3). In case of any error of PMR-two-2IMP, the output of the PMR-two-3NOR gate becomes “.” Otherwise, the output of the PMR-two-3NOR gate becomes “0.”

FIGURE: Error detection for PMR-two-2IMP. a) Circuit diagram of PMR-two-3NOR gate used for error detection. b) Truth table of PMR-two-3NOR gate. c) Simulation results of PMR-two-3NOR success rate as a function of V _Z, when V _P = V _Q = 1.7 V, for all inputs.

However, similar to the PMR-two-2IMP gate, the PMR-two-3NOR gate also suffers from non-ideal factors and requires error control through adjustment of the suitable voltage scheme. Fixing V _P = V _Q = 1.7 V, detailed analyses of the voltage drop across memristors P, Q, and Z for different inputs are shown in Figure S3 (Supporting Information). The unintended nonswitching of the output memristor Z occurs when both inputs are “0”, and the unintended set switching of Z occurs for the other inputs. Through simulation, the success rates of the PMR-two-3NOR gate operation as a function of V _Z are shown in Figure 5c. With the increase in the applied voltage V _Z, the voltage across the output memristor Z gradually increases facilitating the correct execution of the logic for input (0,0), but causes Z to be set incorrectly for the other inputs. Because the accuracy of the PMR-two-3NOR gate cannot be ensured for all inputs, a balance point V _Z = 2.5 V, is chosen to control the error to only occur for the input (0,0), to complete the error detection function.

Because the error rate in case of input (0,0) must be retained in the PMR-two-3NOR gate, the redundancy based on the addition of another output memristor and repetition of the execution of the other PMR-two-3NOR gate should be introduced to guarantee the accuracy of error detection. This is essentially step 3). Therefore, the error detection result is demonstrated by the two-auxiliary memristors Z ₁ and Z ₂ in our scheme (the PMR-two-2IMP error occurs as long as one of them is “1”). Even if the error rate of PMR-two-3NOR is ≈30%, the accuracy of the error detection is more than 90% considering Z ₁ and Z ₂ together.

After using two PMR-two-3NOR gates to complete the error detection, Z ₁, Z ₂, and Q are treated as the input memristors, and Q is also treated as the output memristor to complete the error correction by triggering a composite PMR-three-3OR gate, in which the resistance states of all the three devices are regarded as logic inputs and the resistance state of Q after the operation is the logic output, as shown in Figure  6a. The truth table in Figure 6b shows that once the detection result is “1” in either Z ₁ or Z ₂, the resistance state of memristor Q after the operation will be “1,” otherwise the resistance state of memristor Q after operation remains as the state before operation. The error correction was completed along with the operation of this composite PMR-three-3OR gate. Of course, the control voltages of the PMR-three-3OR gate should also be carefully selected to ensure a high success rate of correction. Fixing V _Z1 = V _Z2 = −0.6 V, the detailed analyses of the voltage drop across memristor Z ₁, Z ₂, and Q for different inputs are shown in Figure S4 (Supporting Information). There is a positive correlation between V _Q and the success rates of the intended switching of Q; however, an increase in the applied voltage V _Q causes an unintended set switching of Q, as shown in Figure 6c. To ensure the correct execution of the logic, the balance point of V _Q is selected as 1.05 V, where the success rate of the PMR-three-3OR gate reaches above 70%.

FIGURE: Error correction for PMR-two-2IMP. a) Circuit diagram of PMR-three-3OR gate used for error detection. b) Truth table of PMR-three-3OR gate, where X denotes the 0/1 don't-care term. c) Simulation results of PMR-three-3OR success rate as a function of V _Q, when V _Z1 = V _Z2 = −0.6 V for all inputs.

The detailed EDS process can be understood from two scenarios. In the first scenario, an error occurs in the PMR-two-2IMP gate. Once the error occurs in the PMR-two-2IMP gate, the input must be (0,0) because of the voltage control. In this case, the state of memristor Q after the PMR-two-2IMP operation will be “0” which is an incorrect result. Thereafter, the two PMR-two-3NOR gates are used for error detection twice with memristors P and Q as logic inputs and Z ₁ and Z ₂ as logic outputs. In this case, at least (90%) one of Z ₁ and Z ₂ will be “1.” Finally, the composite PMR-three-3OR gate is used for error correction. Because one of Z ₁ and Z ₂ is “1” and Q is “0” in this case (error occurs in the PMR-two-2IMP gate), Q is switched to “1” based on the truth table of PMR-three-3OR. The other scenario is that the error does not occur during the execution of the PMR-two-2IMP gate. In this case, the state of memristor Q after the operation of PMR-two-2IMP gate will be “1” when logic inputs are (0,0), (0,1), and (1,1), while memristor Q after the operation of PMR-two-2IMP gate will be “0” when the logic inputs are (1,0). In other words, the states of memristor P and Q after the logic operation will be (0,1), (1,0), or (1,1), as shown in Figure 3b. In the detection process, the outputs of the two PMR-two-3NOR gates (Z1 and Z2) will always be “0,” as shown in Figure 5b. Finally, in the correction process, memristor Q will remain in state “0,” as shown in Figure 6b, in line with our expectations.

For the proposed EDC method, it should be noted that the error control scheme for each stateful logic gate plays a critical role in avoiding the introduction of more errors. For example, because the error of PMR-two-3NOR gate is controlled to only manifest in case of (P = “0,” Q = “0”), the detection for all the other inputs including (P = “0,” Q = “1”), (P = “1,” Q = “0”), and (P = “1,” Q = “1”) would always be correct, that is, Z ₁ = “0,” Z ₂ = “0.” Meanwhile, the error of the PMR-three-3OR gate is controlled to manifest in all cases other than (Z ₁ = “0,” Z ₂ = “0”). Thus, no error is introduced in the PMR-two-2IMP gate for any input, except for (P = “0,” Q = “0”).

Experimental Demonstration

For every test, the entire 1 kb array is read to obtain the information of each memristor before and after the stateful logic operation. During the stateful logic operation, one of the 32 SLs was selected with 2.2 V to turn on the transistor gates in the column, and the other SLs were grounded. The selected BLs are connected to the load resistor R _L, while the other BLs float. According to the stateful logic gate design mentioned earlier, 100 μs voltage pulses were applied to the selected WLs. The experimental demonstrations of PMR-two-2IMP and PMR-two-3NOR gates for all inputs are shown in Figure  7a,c, respectively, where the measured resistance values are displayed in the form of heat maps. Figure 7e,g shows the experimental demonstrations of the PMR-three-3OR gates for the (X, X, 1) and (X, X, 0) inputs, respectively. Figure 7j demonstrates the feasibility of the proposed EDC method for the PMR-two-2IMP logic gate with the (0,0) input.

FIGURE: Experimental verification based on practical devices. a) Example of successful operation of practical PMR-two-2IMP gate. b) Validation of PMR-two-2IMP gate for the (0,0) input 30 times. c) Example of successful operation of practical PMR-two-3NOR gate. d) Validation of PMR-two-3NOR for the (0,0) input 30 times. e) Example of successful operation of the practical composite PMR-three-3OR for the (X, X, 1) input. f) Validation of the composite PMR-three-3OR gate for the (0, 0, 1) input 30 times. g) Successful operation example of the practical composite PMR-three-3OR for the (X, X, 0) input. h) Validation of the composite PMR-three-3OR gate for the (1, 0, 0) input 30 times. i) Validation of the composite PMR-three-3OR gate for the (1, 1, 0) input 30 times. j) Example of successful operation of EDC for the (0, 0) input. k) Repetition of the EDC for the (0, 0) input 30 times.

Furthermore, the success rates of the critical cases for each gate are measured, including the (0,0) input for the PMR-two-2IMP gate shown in Figure 7b, the (0,0) input for the PMR-two-3NOR gate shown in Figure 7d, the (0,0,1) input for the composite PMR-three-3OR gate shown in Figure 7f, the (1,0,0) input for the composite PMR-three-3OR gate shown in Figure 7h, and the (1,1,0) input for the composite PMR-three-3OR gate shown in Figure 7i. Setting the assessment line of HRS (logic “0”) as 80 kΩ and LRS (logic “1”) as 50 kΩ, the statistical results are summarized in Table  1 . The theoretical estimated success rate of PMR-two-2IMP is calculated as follows[Image Omitted. See PDF]where P _{IMP_00}, P _{NOR_00}, P _{OR_100}, and P _{OR_110} represent the success rates mentioned earlier. The calculated success rate is close to the experimentally measured result, as shown in Figure 7k; thus, the proposed method of cascading stateful logic gates can successfully implement the EDC of the PMR-two-2IMP gate with >30% success rate improvement.

Table 1 Test success rate based on practical devices

Logic Operation	Successful Number	Success Rate (%)
NOR logic operation (0,0)	20	66.6667
Composite OR logic operation (1,0, 0)	22	73.3333
Composite OR logic operation (1,1, 0)	26	86.6667
Composite OR logic operation (0,0, 1)	30	100
IMP logic operation (0,0)	16	53.3333
Theoretical error correction success rate		86.5185
Experimentally error correction success rate	26	86.6667

Compared with the previous work,^{[ 36–38 ]} our current strategy uses the stateful logic process to complete the entire detection and correction process that retains the paradigm of in-memory computing. This implies that our work reduces time and energy consumption that is used to read the data out of the crossbar array, although the time efficiency for checking and correcting a single stateful logic gate is lower than that realized in the study conducted by In et al.,^{[ 38 ]} given that the time-wise cascading of several stateful logic gates costs more time than fulfilling a detection and correction function based on a space-wise CMOS circuit. However, when the evaluation is performed based on some data-intensive applications aiming to develop parallelism of the operations, our stateful EDC schemes could exhibit more efficiency. For example, let us assume performing the EDC for the stateful logic gates used in 1024 parallel computing processes across 1024 rows of a crossbar array. In the study conducted by In et al.,^{[ 38 ]} 1024 CMOS EDC circuits were required to serve the computing processes across the 1024 rows simultaneously. If the CMOS EDC circuits are insufficient, the parallel processes need to be changed (partially) into serial, to adjust to the limited resource. This implies that the efficiency of these schemes^{[ 36–38 ]} is limited by the scaling of the CMOS EDC circuits. However, as our proposed strategies are based on stateful logic operations, stateful EDC operations across different rows can be concurrently executed owing to the row/column parallelism characteristic of the crossbar array. This implies that our EDC scheme supports the same-level parallelism as the corrected stateful logic gate. Considering the parallelism paradigm, both the time and energy consumption of our EDC strategies would be more efficient than that of the CMOS circuit-based method. This is mainly because our stateful logic-type EDC retains the benefits of the parallelism of the crossbar array.

In addition, the proposed EDC method has some limitations in that it is not as powerful as the N-modular redundancy method^{[ 36 ]} for the detection and correction of more than one error type, and lowering the applied voltage may require sacrificing the accuracy of the correct results. A balance design of cost and flexibility for highly reliable stateful logic through reliability analysis of memristive stateful-logic-based combinational circuits will be researched further in future work.

Conclusion

A stateful EDC method for the IMP state logic gate (PMR-two-2IMP) was proposed, in which all operations were performed on the memristive crossbar array. For the PMR-two-2IMP gate, the possible error conditions in the logic operation process were discussed, and the potential errors can be controlled by adjusting the voltage application scheme. Thereafter, an EDC scheme based on a PMR-two-3NOR gate and composite PMR-three-3OR gate was proposed. Finally, through HSPICE simulation and experimental tests on TiN/TaO _x /HfO _x /TiN memristors, the feasibility of the designed EDC scheme was verified. The test results confirm that the EDC scheme can significantly improve the success rate of logic operation, although the actual device exhibited large volatility owing to the resistance drift of the device, poor uniformity, and other nonideal factors, and the improvement effect was linked to the performance of the device.

Experimental Section Device Fabrication

A 32 × 32 1 kb 1T1R crossbar array was fabricated through a hybrid integration process using a complementary metal-oxide-semiconductor field effect transistor with a feature size of 180 nm and a bipolar TiN/TaO _x /HfO _x /TiN memristor. After the front-end fabrication in a commercial CMOS foundry where a transistor with a channel width and length of 5 and 350 nm, respectively, was fabricated, the memristor device was installed on the drain side of the transistor in-house in the following steps. A bottom TiN electrode with a thickness of 40 nm was deposited on a polished W plug through reactive sputtering. Thereafter, atomic-layer deposition and physical vapor deposition were employed to grow the 10 nm HfO _x and 50 nm TaO _x switching layers, respectively. A TiN layer with a thickness of 30 nm was deposited as the top electrode. After deposition of the sandwich structure, the dry etching method was used to pattern the device with an effective size of approximately 0.5 × 0.5 μm.

Circuit Platform

The hardware platform contained a Kintex-7 FPGA from Xilinx as the controller of the test system, and the data interaction with the PC was enabled by a high-speed USB 3.0 interface. A two-channel digital-to-analog converter (DAC) that features a 1-GSPS conversion rate and 16-bit resolution, was utilized to generate programmable pulses or DC voltage. The two arbitrary waveform generation channels were connected to the WL and BL for the set and reset operations, respectively. Correspondingly, the response signals from the crossbar array on the BLs were acquired by a 100 MSPS 16-bit analog-to-digital converter (ADC) to read the state of the memristor. To meet the requirements of the proposed logic operation, medium-speed multi-channel DACs were adopted to generate up to 32 independent voltage excitations for the WL, BL, and SL ports. The platform can generate positive or negative programming voltages with a maximum amplitude of 5 V and 1 mV resolution. The pulse width resolution reaches 1 ns, and the minimum rising edge is 10 ns.

Simulation Process of Counting the Success Rate of the Stateful Logic Gate

The cycle-to-cycle and device-to-device variations of the device parameters were considered. Randomized defects in a device matrix were assumed, and the performance of device variation in the pulse test was sampled on 10 devices among the different locations, and each device was tested with 100 cycles of set and reset operations. The TEAM model^{[ 42,43 ]} was modified to fit the statistical distribution of the sampled device variation. The transistor model with a 180 nm feature size was provided by the commercial CMOS foundry. The TEAM and transistor models were used to simulate the success rates of the stateful logic gates.

Acknowledgements

Z.L., C.L., and X.Z. contributed equally to this study. This work was supported by the National Key Research and Development Plan of MOST of China (Grant No. 2019YFB 2205100), National Natural Science Foundation of China (Grant Nos. 61974164, 61701509, and 62074166), and the Science Support Program of the National University of Defense and Technology (Grant Nos. ZK20-06, and ZK20-02).

Conflict of Interest

The authors declare no conflict of interest.

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.