Research on Single-Phase and Three-Phase Compatible Isolated On-Board Charger and Control Technology

Abstract

This paper presents a single-phase and three-phase compatible isolated on-board charger for electric vehicles. The charger is compatible with the single-phase and three-phase AC voltage input and is composed of two-stage circuits. Based on the three-phase six-switch power factor correction (PFC) circuit, by switching on and off, the front stage is transformed into a cascade topology of a totem-pole PFC circuit and boost circuit. The rear stage is a full-bridge LLC resonant converter. In the single-phase or three-phase working mode, the front-stage control strategy is a double closed-loop control. The current inner loop controller is improved for the three-phase six-switch PFC circuit. The PI controller and repetitive controller are connected in parallel to form the current inner loop compound controller, which can effectively reduce the total harmonic distortion of the input current. By using simulation software MATLAB/Simulink, the circuit model was built. The simulation results verify the correctness of the theoretical analysis.

1. Introduction

With the development of the automobile industry, electric vehicles have gradually been promoted. The electric vehicle draws energy from the AC grid through the on-board charger (OBC) and charges the power battery after the electric energy is transformed. Therefore, the OBC is an important part of electric vehicles [1]. The input power supply of OBC mainly includes single-phase AC voltage and three-phase AC voltage. At present, most OBCs mainly work under single-phase input conditions, with low output power and long charging time. With the increase in the capacity of the power battery of new energy vehicles and the demand for faster charging, the market demand for three-phase input high-power car chargers is also increasing [2]. The design of the OBC should be compatible with single-phase and three-phase power inputs so that electric vehicles can meet the use of different power occasions through flexible charging.

The early OBC is the single-stage structure, which has the advantages of a simple circuit structure and convenient control, but its efficiency and power factor are difficult to achieve satisfactory results, and the output voltage range is narrow [3]. Nowadays, the mainstream topology of OBC is mainly composed of a front-stage power factor correction (PFC) circuit and a rear-stage isolated DC–DC circuit. The front-stage PFC circuit can realize PFC, reduce harmonic pollution, and provide the rear-stage DC–DC circuit with a smaller ripple DC bus voltage. The rear stage can output stable and adjustable high-voltage DC supply power to the power battery [4]. Reference [5] proposes a two-stage OBC consisting of a single-phase bridgeless boost PFC circuit and a full-bridge LLC resonant converter. Through the cascade control strategy between modules, the two-stage structure circuit can be started smoothly, the shock in the starting process is eliminated, and the output voltage has no drastic impact. However, the traditional bridgeless PFC circuit has an obvious common mode interference problem. Reference [6] using SiC-MOSFET to design the interleaved parallel totem-pole bridgeless PFC circuit in continuous current mode (CCM) can effectively overcome the common mode interference problem and improve efficiency. Reference [7] designed a 1 kW OBC based on SiC-MOSFET. The front stage of the circuit is a single-ended primary-inductor converter (SEPIC) PFC converter, and the rear stage is a full-bridge LLC resonant converter. Among them, the SEPIC PFC converter can make the DC bus voltage follow the battery pack voltage so that the LLC resonant converter can keep operating near the resonant frequency to realize the optimization of the operating efficiency of the whole machine. The total efficiency from 20% of the rated load to full load is 88.5% to 93.5%. Reference [8] proposes a passive auxiliary converter structure with a three-phase 380 V AC input. The front-stage three-phase six-switch circuit can effectively suppress voltage spikes, and the electric energy can be transferred to the load by itself, thereby reducing the stress of the main circuit. Reference [9] designed a three-phase bidirectional isolated soft-switch OBC. The front stage is a bidirectional 3-phase 4-switch rectifier. Compared with the common three-phase bridge rectifier, the number of switch tubes is reduced by two, which reduces the complexity of the control circuit. The rear stage is a double-bridge series resonant converter with phase-shift control, which can realize bidirectional power flow. However, the topologies proposed in the reference [5,6,7,8,9] can only meet the power supply mode of a single-phase or three-phase input. In recent years, some OBC topologies that can satisfy single-phase and three-phase compatible inputs have been proposed [10,11,12,13]. Reference [10] proposed a modular single-stage electrolytic capacitorless OBC compatible with single-phase and three-phase voltage input, and used relays and decoupling capacitors to transform single-phase and three-phase circuit topologies. Reference [11] proposes a variable front-stage OBC with dual closed-loop interval type II fuzzy control. Based on the interleaved parallel totem pole bridgeless PFC circuit, the third bridge arm and the corresponding control switch are added to design the front stage variable PFC circuit, and the rear stage adopts the full bridge LLC resonant converter. The feasibility of the proposed topology scheme being compatible with a single and three-phase input is verified by simulation experiments. Generally speaking, the DC bus voltage of the single-phase PFC circuit is usually set at about 400 V, and the output DC bus voltage of the three-phase PFC circuit is usually set at about 700~800 V. However, the variable circuit of the front stage proposed in the reference [11] cannot meet the same output voltage of the DC bus, so it will bring inconvenience to the parameter design of the rear stage circuit. Reference [12] considers the efficiency of the rear-stage DC–DC circuit, combined with the requirements of the same DC bus, and uses the relay to achieve a VIENNA topology compatible with different power supply methods. Reference [13] designs the front-stage compatible PFC circuit of OBC. The rectifier has extended voltage gain characteristics in the case of single-phase input and can convert the input AC voltage of 110 V into high-voltage DC of 750 V, realize the same DC bus voltage in the two input modes, and achieve 93.6% efficiency at full load.

As a key technology of OBC, the control strategy directly determines the operation efficiency, battery life, and charging safety of OBC. For the control system of single and three-phase PFC circuits, the double closed-loop PI control strategy using the current inner loop and the voltage outer loop is the most common. However, when the traditional double closed-loop PI control strategy is applied to the three-phase PFC circuit, it is easy to have some problems, such as waveform distortion and an uneven current. Reference [14] adopts a fractional-order PID control strategy to improve steady-state control accuracy and reduce ripple. The results show that the control performance of the system is enhanced, and the steady-state and dynamic performance is improved, but the parameter tuning process is more complicated. Reference [15] proposed an adaptive cosine inner membrane control method to suppress grid-side current harmonics based on traditional PI control, which effectively suppressed the low-frequency harmonics of the grid-side current. Reference [16] analyzed the shortcomings of traditional PI control, where a simplified form of control transfer functions based on the small-signal model was proposed with segmented control action. The methodology has the advantages of both simplified control strategies and segmented PI-repetitive control to achieve high-power factor performance and reduce THD in a broad range of load conditions.

The parameter design of the rear-stage DC–DC circuit is affected by the DC bus voltage output of the front stage. If the DC bus voltage can be the same in the two power supply modes, it will be conducive to the optimal design of the overall circuit. Inspired by the above references, after the rear-stage circuit is determined to be a full-bridge LLC resonant converter, in order to realize the same DC bus voltage under two power supply modes, a two-stage OBC topology that can realize the compatible input of single-phase and three-phase AC voltage is proposed. Based on the three-phase six-switch PFC circuit topology, the front stage transforms into a cascade topology structure of a totem-pole PFC circuit and boost circuit through switching on and off. After the design of compatible inductors and compatible capacitors, the PFC circuit can achieve a compatible input of single-phase and three-phase voltages and provide the same DC input voltage for the rear-stage full-bridge LLC resonant converter. The full-bridge LLC resonant converter establishes an equivalent model through the fundamental wave analysis method and obtains the optimal parameters of the circuit. Aiming at the control strategy of the front-stage three-phase PFC circuit, the current inner loop controller is improved, and the current inner loop PI controller and the repetitive controller are connected in parallel to form the current inner loop compound controller. Compared with the traditional double closed-loop PI control, it can effectively reduce the THD rate of the grid-side current under different load conditions.

2. Topological Structure and Working Principle of the OBC System

Figure 1 shows the basic topology of a single-phase and three-phase compatible isolated OBC. Single-phase and three-phase topology was switched through relays K₁–K₄. When the front stage was a three-phase voltage input, K₁–K₃ was open and K₄ was closed. The topology was a three-phase six-switch PFC circuit. When the front stage was a single-phase voltage input, K₁–K₃ was closed and K₄ was open. The topology was a combination circuit of a totem-pole PFC circuit cascaded boost circuit, and the rear stage was a full-bridge LLC resonant converter. The front-stage PFC circuit included an AC inductor L, field-effect transistors (FETs) S₁–S₆ (SiC-MOSFET), and DC bus capacitances C_dc-s and C_dc. The rear-stage LLC resonant converter included FETs Q₁–Q₈, resonant capacitance C_r, resonant inductor L_r, excitation inductance L_m, transformer T, holding capacitance C_o, and load equivalent resistance R_L.

2.1. Three-Phase Working Mode

Figure 2 shows the charging circuit in the three-phase working mode. The front stage was the three-phase six-switch PFC circuit, which can essentially be equivalent to three pulse-width modulation (PWM) rectifiers. U_a, U_b, and U_c were the three-phase input grid voltage, and the AC inductance L_a = L_b = L_c = L.

The switching function shown in Equation (1) was used to represent an off-conduction state of the FET, and then the operating state of the six FETs of the three-phase bridge arm.

(1)$S_k=\left\{\begin{array}{l}1\begin{array}{cc}& \end{array}\mathrm{The} \mathrm{upper} \mathrm{bridge} \mathrm{arm} \mathrm{is} \mathrm{on}, \mathrm{the} \mathrm{lower} \mathrm{bridge} \mathrm{arm} \mathrm{is} \mathrm{off}\\ 0\begin{array}{cc}& \end{array}\mathrm{The} \mathrm{upper} \mathrm{bridge} \mathrm{arm} \mathrm{is} \mathrm{off}, \mathrm{the} \mathrm{lower} \mathrm{bridge} \mathrm{arm} \mathrm{is} \mathrm{on}\end{array}\right\}k=a,b,c$

It can be seen from Equation (1) that there were a total of eight switch state combinations of S_aS_bS_c = 000, S_aS_bS_c = 001, S_aS_bS_c = 010, S_aS_bS_c = 011, S_aS_bS_c = 100, S_aS_bS_c = 101, S_aS_bS_c = 110, and S_aS_bS_c = 111, corresponding to the path topology of different PWM rectifier converters. By controlling the on–off of S₁–S₆, the input current was in phase with the input voltage, and the waveform was similar to a sine wave, so as to achieve the purpose of PFC.

The rear stage was the full-bridge LLC resonant converter, which converts the high-voltage DC transmitted from the front-stage PFC circuit into high-frequency voltage pulses. The resonant converter converts the high-frequency voltage pulse into sine wave voltage, and finally converts the sine wave voltage into DC voltage output through the rectifier circuit [17]. According to the charging protocol curve of the OBC, the output voltage variation range is controlled by changing the switching frequency of Q₁–Q₄.

2.2. Single-Phase Working Mode

Figure 3 shows the charging circuit in the single-phase working mode. The front stage was the topology of the cascade of the totem-pole PFC circuit and boost circuit. The use of SiC-MOSFET enabled the totem-pole PFC circuit to achieve higher efficiency and can work in CCM. When three-phase AC voltage was input, the DC output voltage after passing through the three-phase six-switch PFC circuit was U_dc, and its rated value was 700 V. When single-phase AC voltage was input, it could output a stable DC voltage U_dc-s after passing through the totem-pole PFC circuit, and its rated value was 400 V. To make the input voltage of the rear-stage full-bridge LLC resonant converter have the same value in the two input modes, a boost circuit was added after the totem-pole PFC circuit to increase the DC voltage from 400 V to 700 V.

When the totem-pole PFC circuit is in a steady-state operation, a power cycle can be divided into four modes, and the working modes of the positive and negative cycles are similar. The two modes of the positive half cycle of the AC input power were taken as an example. For mode one, turn off S₁ and S₃, turn on S₄ and S₆, U_a charges L_a through L_a, S₄, and S₆ loops, and C_dc-s discharges the subsequent circuit. For mode two, turn off S₃ and S₄, turn on S₁ and S₆, U_a and L_a charge C_dc-s through the S₁ and S₆ circuits, and L_a is in a discharged state at this time. When the boost circuit part is in a steady-state operation, it can be divided into two working modes. That is, when S₂ is turned on, U_dc-s charges L_c; when S₂ is turned off, U_dc-s and L_c charge C_dc through the S₅ loop, and L_c is in a discharged state at this time.

3. Parameter Design

The performance indicators of OBC are the main reference for the design of circuit parameters. According to the main performance indicators shown in Table 1, the parameter design should be carried out in the case of the rated output power of single-phase 3.3 kW and three-phase 6.6 kW.

3.1. Parameter Design of the Front-Stage PFC Circuit

• (1). AC inductance L

When the single-phase voltage was input, for the totem-pole PFC circuit, the selection of L required that the maximum value of the input current ripple was less than 10% of the maximum input current. The calculation is expressed as:

(2)$\frac{U_{\text{dc-s}}\cdot T_{\mathrm{sw}}}{8L}<10\%\cdot \frac{\sqrt{2}{P}_{\text{o-s}}}{\eta \cdot U_{\mathrm{in}\_\min }},$

where U_dc-s is the DC bus voltage, U_dc-s = 400 V; T_sw is the switching period, T_sw = 20 μs; P_o-s is the rated output power in single-phase operation, P_o-s = 3.3 kW; η is the efficiency, η = 93%; and U_{in_min} is the minimum input voltage, U_{in_min} = 176 V.

From Equation (2), L > 0.36 mH was obtained.

For the boost circuit, when the inductor current was in the CCM state, the selection of the AC inductor needed to satisfy Equation (3):

(3)$L=\frac{U_{\text{dc-s}}D(1-D)}{\gamma f_{\mathrm{sw}}{I}_{\mathrm{omin}}}=\frac{400\times 0.43\times (1-0.43)}{2\times 50\times {10}^3\times 4}=0.25 \mathrm{mH},$

where D is the duty cycle; γ is the current ripple coefficient; and I_omin is the critical continuous load current.

From Equation (3), if the inductor current was required to work in continuous mode, L > 0.25 mH.

When the three-phase voltage was input, L was determined by the AC current following the performance index and the current harmonic suppression performance index. The calculation is expressed as:

(4)$\frac{U_{\mathrm{m}}{T}_{\mathrm{sw}}(2U_{\mathrm{dc}}-3U_{\mathrm{m}})}{2U_{\mathrm{dc}}\Delta i_{\max }}\le L\le \frac{2U_{\mathrm{dc}}}{3\omega I_{\mathrm{m}}},$

where U_m is the phase voltage fundamental wave, U_m = 311 V; U_dc is the output voltage of the front stage, U_dc = 700 V; I_m is the fundamental peak value of phase current, I_m = 19 A; and Δi_max is the maximum peak value of current ripple, Δi_max = 20%I_m = 3.8 A.

From Equation (4), 0.55 mH ≤ L ≤ 78.2 mH.

Based on the actual situation and simulation experiment, take L = 1 mH.

• (2). DC bus capacitance C_dc-s

When the single-phase voltage was input, for the totem-pole PFC circuit, the choice of the C_dc-s was mainly determined by the low-frequency voltage ripple and the load holding time, which needed to meet Equations (5) and (6). The holding time Δt was the time required for U_dc-s to drop from the rated voltage to β% of the rated voltage after the power outage.

(5)$C_{\text{dc-s}}\ge \frac{P_{\text{o-s}}}{\omega U_{\text{ripple-s}}\cdot U_{\text{dc-s}}^2}=\frac{3300}{2\times \pi \times 50\times 10\times {400}^2}=2626.06 \mathsf{\mu }\mathrm{F},$

where U_ripple-s is the ripple value of the U_dc-s.

(6)$C_{\text{dc-s}}\ge \frac{2P_{\text{o-s}}\Delta t}{U_{\text{dc-s}}^2-{(\beta \%\cdot U_{\text{dc-s}})}^2}=\frac{2\times 3300\times 0.02}{{400}^2-{(0.8\times 400)}^2}=2291.67 \mathsf{\mu }\mathrm{F},$

where Δt = 0.02 s; β% = 80%.

According to Equations (5) and (6), C_dc-s ≥ 2626.06 μF. Based on the actual situation and simulation experiment, take C_dc-s = 2700 μF.

• (3). DC bus capacitance C_dc

In the case of single-phase input voltage, C_dc is part of the boost circuit parameters, and the selection of capacitance mainly controls the output ripple within the specified range. In CCM, the capacitance depends on the output current, switching frequency, and desired output voltage ripple value. Therefore, the capacitance value can be selected according to Equation (7):

(7)$C_{\mathrm{dc}}\ge \frac{I_{\mathrm{o}\max }\cdot D}{f_{\mathrm{sw}}\cdot U_{\mathrm{ripple}}}=\frac{4.71\times 0.43}{50\times {10}^3\times 14}=2.89 \mathsf{\mu }\mathrm{F},$

where I_omax is the maximum output current; and U_ripple is the ripple value of U_dc.

When the three-phase voltage was input, the larger the value of C_dc, the smaller the U_ripple and the stronger the anti-load disturbance ability. However, if the value is too large, it will affect the following performance of the voltage outer loop. Therefore, the selection of C_dc mainly needed to meet the maximum output power and the response time of the voltage loop. The calculation is expressed as:

(8)$C_{\mathrm{dc}}\ge \frac{P_{\mathrm{o}}{T}_{\mathrm{r}}}{2U_{\mathrm{dc}}{U}_{\mathrm{ripple}}}=\frac{6600\times 0.001}{2\times 700\times 14}=336.73 \mathsf{\mu }\mathrm{F},$

where T_r is the response time of the voltage loop, and P_o is the rated output power during three-phase operation.

Based on the actual situation and simulation experiment, take C_dc = 2000 μF.

3.2. Parameter Design of the Rear-Stage Full-Bridge LLC Resonant Converter

Voltage gain is an important characteristic of the LLC resonant converter. A fundamental wave analysis was used to analyze the gain characteristic of the LLC resonant converter [18]. The equivalent circuit of the rear-stage LLC resonant converter is shown in Figure 4.

The normalized voltage gain M can be expressed as:

(9)$M(f_n,L_n,Q_e)=\frac{1}{\sqrt{{(1+\frac{1}{L_n}-\frac{1}{L_n{f}_n^2})}^2+Q_e^2{(f_n-\frac{1}{f_n})}^2}},$

where f_n is the normalized frequency; Q_e is the quality factor; and L_n is the inductance coefficient.

Figure 4 shows that the input impedance Z_in of the rear-stage LLC resonant converter is expressed as:

(10)$Z_{in}=\sqrt{\frac{L_r}{C_r}}[\frac{L_n^2}{1+Q_e^2{f}_n^2{L}_n^2}+j(f_n-\frac{1}{f_n}+\frac{f_n{L}_n}{1+Q_e^2{f}_n^2{L}_n^2})],$

When the imaginary part of Z_in is zero, the maximum quality factor of the converter working in the inductive region can be expressed as:

(11)$Q_{\mathrm{e}\_\max }=\sqrt{\frac{1}{L_n(1-f_n^2)}-\frac{1}{f_n^2{L}_n^2}}.$

• (1). Transformer ratio n

The transformer ratio is expressed as:

(12)$n=\frac{U_{\mathrm{dc}}}{U_{\mathrm{o}\_\mathrm{nor}}}=2,$

where U_{o_nor} is the rated output voltage, U_{o_nor} = 350 V.

• (2). Maximum gain M_max and minimum gain M_min

When U_dc is minimum and U_o is maximum, the maximum gain M_max is expressed as:

(13)$M_{\max }=\frac{n\cdot U_{\mathrm{o}\_\max }}{U_{\mathrm{dc}\_\min }}=1.24,$

where U_{o_max} is the maximum output voltage, U_{o_max} = 420 V; and U_{dc_min} is the minimum front-stage output voltage, U_{dc_min} = 680 V.

When U_dc is maximum and U_o is minimum, the minimum gain M_min is expressed as:

(14)$M_{\min }=\frac{n\cdot U_{\mathrm{o}\_\min }}{U_{\mathrm{dc}\_\max }}=0.78,$

where U_{o_min} is the minimum output voltage, U_{o_min} = 280 V; and U_{dc_max} is the maximum front-stage output voltage, U_{dc_max} = 720 V.

• (3). Inductance coefficient L_n

When the L_n is larger, the amplitude of voltage gain is smaller, causing the working frequency range of the resonant converter to widen. When the L_n is smaller, the excitation current is larger, the turn-off loss of the FET increases, and the efficiency of the converter decreases. Generally, the empirical value of the L_n is between 1–6, and L_n = 2.5 was selected in this design.

• (4). Quality factor Q_e

From the impedance characteristics of the rear-stage LLC resonant converter, the maximum quality factor Q_{e_max} can be expressed as:

(15)$Q_{\mathrm{e}\_\max }=\frac{1}{L_{\mathrm{n}}\cdot M_{\max }}\sqrt{L_{\mathrm{n}}+\frac{M_{\max }^2}{M_{\max }^2-1}}\approx 0.747,$

The value of the quality factor is Q_e = 0.95 Q_{e_max},

(16)$Q_e=0.95\cdot Q_{\mathrm{e}\_\max }\approx 0.71.$

• (5). Maximum operating frequency and minimum operating frequency

Figure 5 exhibits the characteristic operating curve of normalized voltage gain M with normalized frequency f_n when L_n = 2.5.

When the quality factor Q_e = 0, the LLC resonant converter is in a no-load operation state. The intersection of normalized voltage gain curve and minimum voltage gain curve is a₂, and its abscissa is the maximum normalized frequency. The maximum switching frequency is expressed as:

(17)$f_{\mathrm{s}\_\max }=f_{\mathrm{r}}\cdot \sqrt{\frac{1}{L_n\frac{M_{\min }-1}{M_{\min }}+1}}\approx 184 \mathrm{kHz},$

where f_r is the resonant frequency, f_r = 100 kHz.

When the quality factor Q_e = Q_{e_max}, the intersection of the normalized voltage gain curve and the maximum voltage gain curve is a₁, and its abscissa is the minimum normalized frequency. The minimum switching frequency is expressed as:

(18)$f_{\mathrm{s}\_\min }=f_{\mathrm{r}}\cdot \sqrt{\frac{1}{L_n\frac{M_{\max }^2-1}{M_{\max }^2}+1}}\approx 73 \mathrm{kHz}.$

• (6). The equivalent impedance R_ac of the primary side of the transformer

The equivalent impedance of the secondary side circuit of LLC resonant converter converted to the primary side is expressed as:

(19)$R_{\mathrm{ac}}=\frac{8n^2}{{\pi }^2}\cdot \frac{U_{\mathrm{o}\_\mathrm{nor}}^2}{P_{\mathrm{o}}}\approx 60.18 \Omega .$

• (7). Resonant inductor L_r, resonant capacitance C_r, and excitation inductor L_m

According to the value of Q_e and resonant frequency f_r, the expressions and calculated values of L_r and C_r can be obtained with the following:

(20)$L_{\mathrm{r}}=\frac{0.95\cdot Q_{\mathrm{e}\_\max }\cdot R_{\mathrm{ac}}}{2\pi f_{\mathrm{r}}}\approx 68 \mathsf{\mu }\mathrm{H},$

(21)$C_{\mathrm{r}}=\frac{1}{{(2\pi f_{\mathrm{r}})}^2{L}_{\mathrm{r}}}\approx 37.25\mathrm{n}\mathrm{F},$

The excitation inductance L_m is expressed as:

(22)$L_{\mathrm{m}}=L_{\mathrm{n}}\times L_{\mathrm{r}}=170 \mathsf{\mu }\mathrm{H}.$

4. Control Strategy

In the single-phase and three-phase working modes, the control strategy of the front stage was a double closed-loop control. Figure 6 shows the control strategy of OBC in the single-phase working mode. For the totem-pole PFC circuit, the average current control of the double closed-loop PI algorithm was adopted [19]. First, the U_dc-s was sampled and then compared with the reference voltage U_{dc-s_ref} to obtain the output voltage error signal. After passing through the PI controller, the output voltage error signal was multiplied by the input voltage U_in as the reference current i_ref of the inner current loop. The sampled inductor current i_L was compared with the i_ref and then passed through the current loop PI controller, which was then compared with the sawtooth wave in the PWM module to generate a specific duty cycle drive signal. The boost circuit adopted the traditional double closed-loop PI control. The current loop was the inner loop, and the voltage loop was the outer loop, which increased the DC bus voltage from 400 V to 700 V.

The rear-stage LLC resonant converter operated in constant-voltage charging mode and constant-current charging mode. Together, the converter only needed to control one variable, namely the output voltage U_o or output current I_o. Although the dynamic response of the single-loop control is poor, the output current and voltage will not change greatly in the charging process, so the single-loop control can meet the charging requirements.

When the charging circuit was in the three-phase working mode, for the three-phase PFC circuit, there were problems such as waveform distortion and uneven current flow under the traditional double closed-loop PI control strategy. The current inner loop controller was improved and a repetitive controller was added to achieve a better harmonic suppression effect. The PI controller and the repetitive controller were connected in parallel to form the current inner loop compound controller, which can effectively reduce the THD rate of the current on the grid side.

Figure 7 shows the control strategy of the OBC in the three-phase working mode. The difference between the DC voltage reference U_{dc_ref} and the U_dc was made, and the error signal obtained passed through the PI regulator of the voltage outer loop, whose output was the given value of i_d. After coordinated transformation and phase-locked loop (PLL) algorithm, the d-axis and q-axis components e_d and e_q and phase signal ωt of ac side voltage U_a, U_b, and U_c were respectively obtained. The AC side current i_a, i_b, and i_c also went through the corresponding coordinate transformation, and the d- and q-axis feedback quantities i_d and i_q were obtained. The obtained i_d and i_q were differenced with the reference values i_d* and i_q*, and the error value was obtained through the current inner loop repetitive controller and the decoupling algorithm to obtain the output of u_d and u_q. After the u_d and u_q went through the reverse park transformation, the control signal of the power switching device was obtained through the space vector pulse-width modulation (SVPWM) algorithm to achieve the PFC function.

4.1. Front-Stage Three-Phase PFC Circuit Current Inner Loop Compound Controller

Figure 8 shows the design of the current inner loop compound controller with the d-axis as the analysis object. i_d* is the d-axis reference of the AC side current, i_d is the d-axis output of the AC side current, e(z) is the error between i_d* and i_d, C(z) is the compensator, P(z) is the transfer function of the discretized controlled object, d(z) is the disturbance signal, and PI(z) is the discretized PI regulator. When the d(z) is ignored, the error e(z) is acted by the PI regulator and repetitive controller together, and the generated control signal acts on the controlled object P(z).

4.1.1. Design of Repetitive Controller

Repetitive control is a new control method based on the internal model principle, which can effectively restrain periodic disturbance error. In the three-phase PFC circuit, due to the influence of the power tube dead zone time, periodic errors of the power grid current will occur, thus increasing the harmonic component of the power grid current. For periodic errors in the three-phase PFC circuit, although the PI controller will compensate and adjust, the effect is not ideal [20].

The transfer function of the repetitive controller is expressed as:

(23)$\mathrm{H}(z)=\frac{z^{-N}·C(z)}{1-\mathrm{Q}(z)z^{-N}},$

where Q(z) = 0.97; N is the sampling times of one cycle; and C(z) is the compensator.

The transfer function of compensator C(z) is expressed as:

(24)$C(z)=k_{\mathrm{r}}\cdot z^k,$

where k_r is the amplitude compensation coefficient; and z^k is the phase compensation link.

k_r has a greater influence on the error convergence rate, and the value range of k_r is 0 < k ≤ l. The larger the value, the faster the error convergence, so k_r is taken as 1.

According to Equations (23) and (24), the transfer function of the repetitive controller can be obtained by:

(25)$\mathrm{H}(z)=\frac{z^{-N+k}}{1-\mathrm{Q}(z)\cdot z^{-N}}.$

4.1.2. Design of Current Inner Loop PI Controller

After feedforward decoupling, the d-axis and q-axis components are independent of each other. Since the current inner loop adopts digital control, its sampling and calculation process will have a time-delay effect. Figure 9 shows the control system of the current inner loop, where e^−sTs is the calculation delay link, (1 − e^−sTs)/s is the zero-order hold link, and 1/(R_s + sL) is the controlled object of the current inner loop.

The transfer function G(s) of the digital controller consisting of the calculation delay link and the zero-order hold link is expressed as:

(26)$G(s)=\frac{1}{T_{\mathrm{s}}}\cdot {\mathrm{e}}^{-s{T}_{\mathrm{s}}}\cdot \frac{1-{\mathrm{e}}^{-s{T}_{\mathrm{s}}}}{s}\approx {\mathrm{e}}^{-1.5s{T}_{\mathrm{s}}}\approx \frac{1}{1+1.5s{T}_{\mathrm{s}}},$

The current inner loop transfer function G_oi(s) can be expressed as:

(27)$G_{\mathrm{oi}}(s)=\frac{k_{\mathrm{ii}}(\mathrm{A}s+1)}{R_{\mathrm{s}}s(1+1.5s{T}_{\mathrm{s}})(1+s\frac{L}{R_{\mathrm{s}}})},$

where L is the filter inductance; R_s is the parasitic resistance of filter inductor; and A = k_ip/k_ii is the parameter ratio of the current inner loop PI regulator.

According to the classic control theory, the zero point of the PI regulator is introduced into the current inner loop gain to offset the complex poles in the system, making the system a type I system [21]. When A = L/R_s, the expression of current inner loop transfer function G_oi(s) can be simplified as:

(28)$G_{\mathrm{oi}}(s)=\frac{k_{\mathrm{ii}}}{R_{\mathrm{s}}s(1+1.5s{T}_{\mathrm{s}})},$

Using the setting method of the second-order system, and taking the damping coefficient ζ = 0.707, then:

(29)$\{\begin{array}{l}{\omega }_{\mathrm{n}}^2=\frac{k_{\mathrm{ii}}}{1.5R_{\mathrm{s}}{T}_{\mathrm{s}}}\\ 2\zeta {\omega }_{\mathrm{n}}=\frac{1}{1.5T_{\mathrm{s}}}\end{array},$

where ω_n is the undamped oscillation frequency; ζ is the damping coefficient; and T_s is the sampling time of the current inner loop.

Through calculation, the closed-loop transfer function G_ci(s) of the current inner loop can be expressed as:

(30)$G_{\mathrm{ci}}(s)=\frac{G_{\mathrm{oi}}(s)}{1+G_{\mathrm{oi}}(s)}\approx \frac{1}{1+6s{T}_{\mathrm{s}}}.$

4.2. Front-Stage Three-Phase PFC Circuit Voltage Outer Loop Controller

The output current of the DC bus can be expressed as:

(31)$i_{\mathrm{dc}}=0.75\cdot i_{\mathrm{d}}\cdot m\cdot \cos (\theta ),$

where m is the modulation coefficient of the pre-stage PFC circuit; and θ is the initial phase angle of the switching function.

Figure 10 is the voltage outer loop control block diagram, where G_ci(s) is the closed-loop transfer function of the current inner loop, k_vp and k_vi are the parameters of the voltage outer loop PI regulator, T_v is the sampling time of the front-stage output voltage, and 1/sC_dc is the controlled object of the voltage outer loop.

Figure 11 is the simplified voltage outer loop control block diagram, combining the time constant 1.5 T_v of the digital controller in the voltage outer loop with the time constant 6 T_s in G_ci(s) to simplify the voltage outer loop control system.

The voltage outer loop transfer function G_ov(s) can be expressed as:

(32)$G_{\mathrm{ov}}(s)=\frac{0.75\cdot k_{\mathrm{vi}}(\frac{k_{\mathrm{vp}}}{k_{\mathrm{vi}}}s+1)}{s^2{C}_{\mathrm{dc}}[(6T_{\mathrm{s}}+1.5T_{\mathrm{v}})s+1]},$

Let ω₁ = k_vi/k_vp and ω₂ = 1/(6 T_s + 1.5 T_v), then the frequency width of the voltage outer loop h is expressed as:

(33)$h=\frac{{\omega }_2}{{\omega }_1}=\frac{k_{\mathrm{vp}}}{k_{\mathrm{vi}}(6T_{\mathrm{s}}+1.5T_{\mathrm{v}})},$

According to the parameter design of a typical type II system [22], Equation (34) can be obtained:

(34)$\frac{0.75k_{\mathrm{vi}}}{C_{\mathrm{dc}}}=\frac{1}{h\sqrt{h}{(6T_s+1.5T_v)}^2},$

where T_v = 1 ms and the sampling time of the current inner loop T_s = 0.1 ms.

According to Equations (33) and (34), the parameters of the voltage outer loop PI regulator k_vp and k_vi are:

(35)$\{\begin{array}{l}{k}_{\mathrm{vi}}=\frac{C_{\mathrm{dc}}}{330.75\times h\sqrt{h}{T}_{\mathrm{s}}^2}\\ k_{\mathrm{vp}}=\frac{C_{\mathrm{dc}}}{15.75\times \sqrt{h}{T}_{\mathrm{s}}}\end{array}.$

4.3. Control Strategy of Rear-Stage Full-Bridge LLC Resonant Converter

Since the LLC resonant converter contains a variety of working modes, a corresponding state-space model is established by using the piecewise linear space method, and nonlinear terms in system equations are linearly approximated by using the extended description function method [23]. The transfer function expression from switching frequency to the output voltage of the full-bridge LLC resonant converter is obtained as follows:

(36)$G_{\mathrm{vf}}(s)=\frac{K_{\mathrm{vf}}(s{C}_{\mathrm{o}}{r}_{\mathrm{c}}+1)}{(s{C}_{\mathrm{o}}{R}_{\mathrm{L}}+1)(\frac{s^2}{f_{\mathrm{s}}^2}+\frac{s}{f_s\cdot Q_{\mathrm{e}}}+1)},$

where f_s is the operating frequency of the full-bridge LLC resonant converter, f_s = 85 kHz; Q_e is the quality factor of the resonant converter; C_o is the output holding capacitance; R_L is the equivalent output load; and r_c is the series equivalent resistance of the holding capacitance, r_c $\approx$ 0.4 Ω.

(37)$K_{\mathrm{vf}}=\frac{u_{\mathrm{dc}}}{n}[\frac{f_{\mathrm{r}}^3{f}_{\mathrm{s}}(1+\frac{1}{L_{\mathrm{n}}}-\frac{f_{\mathrm{r}}}{L_{\mathrm{n}}{f}_{\mathrm{s}}})}{2\pi L_{\mathrm{n}}{f}_{\mathrm{r}}^2{f}_{\mathrm{s}}^3{[(1+\frac{1}{L_{\mathrm{n}}}-\frac{f_{\mathrm{r}}}{L_{\mathrm{n}}{f}_{\mathrm{s}}})+Q_{\mathrm{e}}^2{(\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}-\frac{f_{\mathrm{r}}}{f_{\mathrm{s}}})}^2]}^{\frac{3}{2}}}+\frac{L_{\mathrm{n}}{Q}_{\mathrm{e}}^2(f_{\mathrm{s}}^2-f_{\mathrm{r}}^2)(f_{\mathrm{s}}^2+f_{\mathrm{r}}^2)}{2\pi L_{\mathrm{n}}{f}_{\mathrm{r}}^2{f}_{\mathrm{s}}^3{[(1+\frac{1}{L_{\mathrm{n}}}-\frac{f_{\mathrm{r}}}{L_{\mathrm{n}}{f}_{\mathrm{s}}})+Q_{\mathrm{e}}^2{(\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}-\frac{f_{\mathrm{r}}}{f_{\mathrm{s}}})}^2]}^{\frac{3}{2}}}],$

Equation (37) is simplified to obtain K_vf = 7.77 × 10⁻⁵.

According to Equations (36) and (37), the transfer function from the switching frequency to the output voltage of the LLC resonant converter can be expressed as:

(38)$G_{\mathrm{vf}}(s)=\frac{7.77\times 10^{-5}(1.2\times {10}^{-5}s+1)}{(5.29\times 10^{-4}s+1)(\frac{s^2}{7.23\times 10^9}+\frac{s}{6.03\times 10^4}+1)},$

According to Equation (38), the Bode diagram of the transfer function without adding the voltage PI controller is obtained, as shown in Figure 12.

Since the LLC resonant converter before correction is a 0-type system, it is necessary to add a PI controller to improve the system type, so that the mid-frequency band of the system drops at a slope of −20 dB/dec and crosses the 0 dB line, thereby improving the phase margin of the system and ensuring that the system has good stability.

In the constant voltage charging mode, the control block diagram of the LLC resonant converter after adding the voltage PI controller is shown in Figure 13.

The voltage outer loop PI controller can be expressed as:

(39)$\mathrm{P}{\mathrm{I}}_{\mathrm{v}}(s)=\frac{3.62\times {10}^7(1+1.1\times {10}^{-4}s)}{s},$

In the constant voltage charging mode, the transfer function of the LLC resonant converter with the voltage PI controller is expressed as:

(40)${\phi }_{\mathrm{LL}{\mathrm{C}}_{\mathrm{v}}}(s)=\mathrm{P}{\mathrm{I}}_{\mathrm{v}}(s)\cdot G_{\mathrm{vf}}(s),$

From Equation (40), the system transfer function of the voltage PI controller is obtained, and the Bode diagram is shown in Figure 14.

It can be seen from Figure 14 that the LLC resonant converter has a crossing frequency of 355 Hz and a phase margin of 63.2°, which can meet the requirements of the stable regulation of the system and has a relatively stable middle frequency bandwidth. When the LLC resonant converter works in constant voltage mode, the working frequency of the primary side FET has a small variation range, and its output voltage range is 280–420 V. The transfer function of the LLC resonant converter has a small change, which is conducive to the design of a single-loop controller.

5. System Simulation Analysis

The circuit was simulated and analyzed in MATLAB/Simulink to examine the correctness and feasibility of the proposed single-phase and three-phase compatible isolated OBC and the control effect of the improved control strategy under the three-phase input condition. Figure 15 shows the main circuit model and control model built in the simulation software. The simulation parameters of the OBC are shown in Table 2.

5.1. Single-Phase Input Mode Simulation Waveform

• (1). Grid current waveform

Figure 16 shows the waveform of the power grid voltage and current under the single-phase input condition. It can be seen from the figure that the sine characteristic of the power grid current is good, the frequency and phase of power grid voltage are the same, and the circuit has a high-power factor. Figure 17 shows the power factor value, which is 0.997, and the correction effect is ideal.

• (2). Output voltage waveform

Figure 18 shows the output waveform of DC bus voltage U_dc-s. After 0.1 s, the voltage is stable at about 400 V. The control effect is good and meets the design requirements. By amplifying the waveform of the labeled part, the peak-to-peak value of the voltage ripple is about 14 V, which is less than the ripple rate requirement of 5%.

Figure 19 shows the output waveform of the front-stage output voltage U_dc. The voltage reaches stability after rapidly rising to 700 V and the overshot is small. The voltage ripple peak in the amplification area is about 1 V, which is far less than the ripple rate requirement, indicating that the front-stage circuit meets the design requirements under the single-phase working mode.

5.2. Three-Phase Input Mode Simulation Waveform

• (1). Power grid current wave type

As shown in Table 3, under the condition that all parameters are the same, the THD of the input current is compared between current inner loop PI control and current inner loop parallel PI-repetitive control under full load, half load, and 25% load, respectively.

It can be seen from Table 3 that under different load conditions, the input current THD with parallel PI-repeat control is always lower than that with PI control. Taking the full load case as an example, the input current waveform and the THD analysis figures of current inner loop with PI control and parallel PI-repetitive control are shown in Figure 20 and Figure 21, respectively. By comparing Figure 20a and Figure 21a, it can be seen that after the controller of current inner loop is improved, the waveform of input current is smoother. Compared with Figure 20b and Figure 21b, it can be seen that the THD of the current inner loop parallel PI-repetitive control is significantly reduced, indicating that the repetitive control has a better inhibition effect on the periodic error.

Figure 22 shows the waveform of the power grid voltage and current under the three-phase input condition. In the steady-state operation, the three-phase input current is a smooth sine wave shape after compound control, and the current distortion is small. The phase of a-phase input current is always consistent with the phase of input voltage. Figure 23 shows the power factor value. It can be seen from the figure that the circuit works in a state of high-power factor, and the power factor value is higher than 0.99, which meets the expected setting requirements.

• (2). Output voltage waveform

Figure 24 shows the output bus voltage waveform of the three-phase PFC circuit. After about 0.1 s, the system enters a steady state, and the bus voltage follows the given voltage value, and the overshoot is small. At the same time, the ripple value of the voltage is about 0.2 V, which is far less than the ripple rate of 5% and meets the design expectation.

5.3. Simulation Waveform of Rear-Stage Full-Bridge LLC Resonant Converter

Figure 25 shows the driving waveform of the FET of the LLC resonant converter when the charger is working. U_gs-1 is the driving signal of Q₁ and Q₃, and U_gs-2 is the driving signal of Q₂ and Q₄. On the same bridge arm, the driving signals of two sets of FETs are complementary and have dead time. Figure 26 shows the waveforms of the drain-source voltage and the driving voltage of the MOSFET. After the drain-source voltage U_{ds_1} of the MOSFET drops to zero, the corresponding driving voltage U_{gs_1} begins to rise, and the primary side MOSFET realizes zero voltage switching (ZVS).

Figure 27 shows the waveform of the resonant capacitance voltage U_Cr, resonant current I_Lr, and the central point voltage U_ab of the original side when no load. At this point, the resonant current appears as a triangular wave shape. When the voltage at the central point of the primary side falls, the resonant current is greater than zero, indicating that the primary side FETs have ZVS characteristics.

Figure 28 shows the waveform of the resonant capacitance voltage U_Cr, resonant current I_Lr, and the central point voltage U_ab of the original side at full load. When the switching frequency of the LLC resonant converter is equal to the resonant frequency, the waveform of the resonant current is approximately sine wave. When the voltage at the central point of the primary side falls, the resonant current is greater than zero, and the resonant cavity presents sensibility, and the primary side FETs can realize ZVS.

Figure 29 shows the rated output voltage waveform of the LLC resonant converter at full load. At about 0.02 s, the output voltage can reach a stable value of 350 V. When 50% load jump is set at 0.3 s, the output voltage will have a small fluctuation, which can be restored to a stable value after about 0.08 s.

6. Conclusions

This paper proposes a two-stage isolated OBC that can be compatible with single-phase and three-phase AC voltage inputs. By switching the relay on and off, the front stage can realize the switching of single-phase and three-phase PFC circuits. The rear-stage circuit is the full-bridge LLC resonant converter. When the single-phase voltage input, the front stage circuit is the totem pole PFC circuit cascade boost circuit; When the three-phase voltage input, the front stage circuit is the three-phase six-switch PFC circuit. The control strategy of the three-phase PFC circuit is optimized, and a repetitive controller is introduced into the current inner loop to reduce the harmonic distortion rate of input current. By designing and calculating the parameters of the OBC, the effectiveness of the proposed circuit structure and control strategy is verified in simulation software. The simulation results show that the vehicle charger can realize the single-phase and three-phase AC voltage input and realize the PFC function, the DC output voltage level of the front stage is the same under the two working conditions. At the same time, the rear-stage LLC resonant converter can realize soft switching in the full load range. After the repetitive controller is introduced into the current inner loop of the three-phase PFC circuit, the waveform of input current is improved, and the THD of input current is lower than that of current inner loop PI control under different load conditions, which has a good control effect.

Author Contributions

Conceptualization, K.Z.; methodology, K.Z., S.-M.C., N.-Z.J. and D.-Y.S.; software, S.-M.C.; supervision, K.Z., N.-Z.J. and D.-Y.S.; writing—review and editing, S.-M.C. All authors have read and agreed to the published version of the manuscript.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Conflicts of Interest

The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Figures and Tables

Figure 1. Single-phase and three-phase compatible isolated on-board charger (OBC).

Figure 2. Three-phase working mode.

Figure 3. Single-phase working mode.

Figure 4. Equivalent circuit of LLC resonant converter.

Figure 5. Normalized voltage gain curve.

Figure 6. Single-phase working mode control strategy.

Figure 7. Three-phase working mode control strategy.

Figure 8. Current inner loop composite control block diagram.

Figure 9. Current inner loop control block diagram.

Figure 10. Control block diagram of voltage outer loop.

Figure 11. Simplified voltage outer loop control block diagram.

Figure 12. Bode diagram of transfer function without voltage PI controller.

Figure 13. Control block diagram of adding voltage PI controller.

Figure 14. Bode diagram of transfer function with voltage PI controller.

Figure 15. Simulation model of OBC.

Figure 16. Power grid voltage and current waveform (single-phase input).

Figure 17. Power factor (single-phase input).

Figure 18. DC bus voltage Udc-s.

Figure 19. Front-stage output voltage Udc.

Figure 20. Current inner loop with PI control. (a) the waveform of the input current; (b) the THD analysis of the input current.

Figure 21. Current inner loop with parallel PI-repetitive control. (a) the waveform of the input current; (b) the THD analysis of the input current.

Figure 22. Power grid voltage and current waveform (three-phase input).

Figure 23. Power factor (three-phase input).

Figure 24. Output bus voltage.

Figure 25. FET driving waveform.

Figure 26. FET drain-source voltage and driving voltage waveform.

Figure 27. Voltage waveform of the resonant capacitance, resonant current, and the voltage waveform at the center point of the original side of LLC at no-load condition.

Figure 28. Voltage waveform of the resonant capacitance, resonant current, and the voltage waveform at the center point of the primary side of LLC at full-load condition.

Figure 29. Waveform of rated output voltage.

Table 1

Main performance indicators of on-board charger (OBC).

Performance Indicator	Value
Input phase voltage range (Uin)	176~264 V
Input voltage frequency range (f)	45~65 Hz
DC bus voltage (Udc-s)	400 V
Front-stage output voltage (Udc)	700 V
Output voltage range (Uo)	280~420 V
Rated output voltage (Uo_nor)	350 V
PFC circuit switching frequency (fsw)	50 kHz
Power factor	≥0.99
Efficiency (η)	≥93%

Table 2

The OBC simulation parameters.

Simulation Parameter	Value
Filter inductance (L)	1 mH
DC bus capacitance (Cdc-s)	2700 μF
DC bus capacitance (Cdc)	2000 μF
Resonant inductance (Lr)	68 μH
Resonant capacitance (Cr)	37.25 nF
Excitation inductance (Lm)	170 μH
Output holding capacitance (Co)	4000 μF

Table 3

Under different load conditions, the THD of the input current obtained by PI control and PI-repetitive control.

Load	Current Inner Loop PI Control	Current Inner Loop PI-Repetitive Control
	THD (%)	THD (%)
Full Load	3.82	2.41
Half Load	6.74	4.36
25% Load	10.82	8.65

References

1. Alireza, K.; Michael, D. Global trends in high-power on-board chargers for electric vehicle. IEEE Trans. Veh. Technol.; 2019; 68, pp. 3306-3324.

2. Andreas, T.; Peter, B.A.; Tim, U.; Chresten, T.; Mattia, M. Electrification of personal vehicle travels in cities-Quantifying the public charging demand. eTransportation; 2021; 9, 100125.

3. Mi, N.; Sasic, B.; Marshall, J.; Tomasiewicz, S. A novel economical single stage battery charger with power factor correction. Proceedings of the 18th Annual IEEE Applied Power Electronics Conference and Exposition; Miami, FL, USA, 9–13 February 2003.

4. Zhao, W.H.; Shen, Y.X. Review on the research of electric vehicle on-board charger topologies. Control Eng. China; 2019; 26, pp. 29-36.

5. Dai, H.C.; Ye, X.T.; Shou, Y.L.; Wang, Z.S. Research on control strategy of on-board charger (OBC) based on PFC and LLC two-level structure. Electr. Eng.; 2020; 11, pp. 38-42.

6. Park, M.-H.; Baek, J.; Jeong, Y.; Moon, G.-W. An interleaved totem-pole bridgeless boost PFC converter with soft-switching capability adopting phase-shifting control. IEEE Trans. Power Electron.; 2019; 34, pp. 10610-10618. [DOI: https://dx.doi.org/10.1109/TPEL.2019.2900342]

7. Shi, C.; Wang, H.Y.; Dusmez, S.; Khaligh, A. A SiC-based high-efficiency isolated onboard PEV charger with ultrawide DC-link voltage range. IEEE Trans. Ind. Appl.; 2017; 53, pp. 501-511. [DOI: https://dx.doi.org/10.1109/TIA.2016.2605063]

8. Meng, T.; Ben, H.Q.; Wang, X.S. A passive flyback auxiliary circuit with integrated transformer suitable for three-phase isolated full-bridge boost PFC converter. IEEE Trans. Power Electron.; 2016; 31, pp. 4995-5003. [DOI: https://dx.doi.org/10.1109/TPEL.2015.2478896]

9. Ebrahimi, S.; Taghavi, M.; Tahami, F.; Oraee, H. Integrated bidirectional isolated soft-switched battery charger for vehicle-to-grid technology using 4-Switch 3Φ-rectifier. Proceedings of the IECON 39th Annual Conference of the IEEE Industrial Electronics Society; Vienna, Austria, 10–13 November 2013.

10. Kim, H.; Park, J.; Kim, S.; Hakim, R.M.; Belkamel, H.; Choi, S. A single-stage electrolytic capacitor-less EV charger with single- and three-phase compatibility. IEEE Trans. Power Electron.; 2022; 37, pp. 6780-6791. [DOI: https://dx.doi.org/10.1109/TPEL.2021.3127010]

11. Zhang, T.S.; Peng, Y.Q.; Zhao, Y.Y.; Huang, X.R.; Liu, X.R. Research on double closed loop interval Type II fuzzy control model of front-stage variable on-board charger. Control Eng. China; 2022; pp. 1-13. early access [DOI: https://dx.doi.org/10.14107/j.cnki.kzgc.20220093]

12. Zhou, S.Y. Research on Single and Three-Phase Compatible VIENNA Rectifier. Master’s Thesis; Nanjing University of Aeronautics and Astronautics: Nanjing, China, 2020.

13. Sadilek, T.; Jang, Y.; Hao, S.; Jia, M.; Barbosa, P.; Husain, I. A new PFC CCM boost rectifier with extended gain and reduced voltage switching for 1-ph/3-ph universal input on-board charger for electric vehicles. Proceedings of the 5th IEEE Applied Power Electronics Conference and Exposition; Phoenix, AZ, USA, 14–17 June 2021.

14. Cao, J.F.; Xiong, H.J.; Lei, D.M. LCL-type grid-connected inverter based on fractional-order PID control. Proceedings of the 3rd International Conference on Industrial Informatics-Computing Technology, Intelligent Technology, Industrial Information Integration (ICIICII); Wuhan, China, 2–3 December 2017.

15. Liu, B.; Ben, H.; Bai, Y.; Sun, S. Analysis and suppression of current harmonics in grid side of PWM rectifiers during light load. Trans. China Electrotech. Soc.; 2017; 31, pp. 162-168.

16. Ali, M.; Wang, L.; Chen, G. Design and control aspect of segmented proportional integral-repetitive controller parameter optimization of the three-phase boost power factor correction rectifier. Int. J. Circuit Theory Appl.; 2021; 49, pp. 554-575. [DOI: https://dx.doi.org/10.1002/cta.2896]

17. Zhang, J.; Wang, J.; Zhang, G.; Qian, Z. A hybrid driving scheme for full-bridge synchronous rectifier in LLC resonant converter. IEEE Trans. Power Electron.; 2012; 27, pp. 4549-4561. [DOI: https://dx.doi.org/10.1109/TPEL.2011.2180027]

18. Deng, J.; Li, S.; Hu, S.; Mi, C.; Ma, R. Design methodology of LLC resonant converters for electric vehicle battery Chargers. IEEE Trans. Veh. Technol.; 2014; 63, pp. 1581-1592. [DOI: https://dx.doi.org/10.1109/TVT.2013.2287379]

19. Zhang, Z.G.; Li, S.F.; Li, X.; Cheng, P.M.; Luo, Q.M. A high efficiency totem-pole bridgeless PFC converter in CCM mode. Proc. CSEE; 2022; 42, pp. 1957-1968.

20. He, L.; Zhang, K.; Xiong, J. A repetitive control scheme for harmonic suppression of circulating current in modular multilevel converters. IEEE Trans. Power Electron.; 2015; 30, pp. 471-481. [DOI: https://dx.doi.org/10.1109/TPEL.2014.2304978]

21. Zhou, K.; Fang, H.L.; Liu, Y. Driving–charging integrated controller for electric vehicles. IEEE Access; 2022; 10, pp. 66545-66563. [DOI: https://dx.doi.org/10.1109/ACCESS.2022.3185261]

22. Yang, Y.; Zhang, J. Phase compensation resonant control strategy for three-phase PWM converter. Electr. Mach. Control; 2013; 17, pp. 43-49.

23. Zhou, K.; Yuan, C.X.; Sun, D.Y.; Jin, N.Z.; Wu, X.G. Parameter adaptive terminal sliding mode control for Full-Bridge DC-DC converter. PLoS ONE; 2021; 16, e0247228. [DOI: https://dx.doi.org/10.1371/journal.pone.0247228] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/33630901]