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Abstract
In the history of the development of OTP memory, many existing structures of fuse breakdown devices used a narrow wire of metal or poly-silicide wire. On the other hand, anti-fuse breakdown devices formed an electrically conductive path permanently in the dielectric after a large external electric field applying on the gate. What this thesis is going to discuss is the problem of too large programming voltage and layout area for the design of one-time programming memory. Our team proposed a new programming method, using avalanche breakdown incurred at the source/drain PN junction, which can effectively reduce the programming voltage, and also used the common-line design in the circuit to reduce the required area and enhance the competitiveness of this design on read-only memory components.
Therefore, in this thesis, we used 14nm finFET to design embedded one-time programming memory. First, we keep the gate and substrate floating in a p-channel finFET, applying a large bias to the source or drain, and ground the other side, so that the PN junction between the drain or source to the substrate has a very large electrical potential. From the concept of the energy band diagram, it can be known that when the source or drain side is uplifted, a small number of electrons can tunnel from below the valence band to the channel. During the tunneling process, it will hit the electron-hole pair in the path, high-level current occurs when the impact ionization happens in the depletion region of channel. It further leads to the avalanche breakdown because of the higher reversed bias, which caused the current to drop to 0.1pA level originally at 0.1mA level, from which different two states can be used as the one-time programming memory.
Random Telegraph Noise technology has also been used to explore the main distribution of trap in the programming mode of the device, so as to explain that this programming mechanism occurs near the PN junction. In terms of circuit design, the concept of common line method is used. Bit lines and source lines of the same voltage are required for different cells, which can greatly reduce power consumption and layout area. Because of this circuit architecture, the disturbance test in the programming and reading modes have also been discussed more often.
Finally, based on this new scheme, we designed an embedded one-time programming memory, which has a larger on/off current ratio compared to that of reported results. In addition to the above, we also explored the relationship between the different channel lengths and the programming voltage, and found that the channel length is proportional to the programming voltage. The longer of the channel length becomes, the higher of the programming voltage will be. It means that long channel length can tolerate the avalanche breakdown, which can greatly reduce power consumption in the future. Finally, an embedded one-time programming memory has been demonstrated successfully on a 14nm FinFET platform to meet the requirements of security applications in IoT era.
